Table of Contents
- Contents
- Revision History
- 1 Introduction
- 2 Low Power Features
- 3 Electrical Specifications
- 4 Package Mechanical Specifications and Pin Information
- 5 Thermal Specifications and Design Considerations
Intel 360 User Manual
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Document Number: 303110-008
Intel® Celeron® M Processor
on 90 nm Process
Datasheet
January 2007
2Datasheet
IINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS
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TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for
use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Celeron® M processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Δ Intel pr ocessor n umbers are not a measur e of per formance . Proc essor nu mbers d ifferen tiate f eatures w ithin each pr ocesso r famil y, not across different
processor families. See www.intel.com/products/processor_number for details.
Intel, Celeron, MMX, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other
countries.
*Other names and brands may be cl aimed as the property of others.
Copyright© 2004–2007, In tel Corporation. All rights reserved.
Datasheet 3
Contents
1Introduction..............................................................................................................7
1.1 Terminology .......................................................................................................8
1.2 References .........................................................................................................8
2 Low Power Features ................................................................................................ 11
2.1 Clock Control and Low Power States .................................................................... 11
2.1.1 Normal State ......... ........... .. .. .. ........... .. .. ..................... .. .. ..................... .. 11
2.1.2 AutoHALT Power-D own State ................... ............................... ... .. .. .......... 11
2.1.3 Stop-Grant State........................................................... ......................... 11
2.1.4 HALT/Grant Snoop State ......................................................................... 12
2.1.5 Sleep State ........................................................................................... 12
2.1.6 Deep Sleep State ................................................................................... 13
2.2 FSB Low Power Enhancements ............................................................................ 13
2.3 Processor Power Status Indicator (PSI#) Signal..................................................... 14
3 Electrical Specifications........................................................................................... 15
3.1 Power and Ground Pins ...................................................................................... 15
3.1.1 FSB Clock (BCLK[1:0]) and Processor Clocking........................................... 15
3.2 Voltage Identification and Power Sequencing ........................................................ 15
3.3 Catastrophic Therm al Pro tec tion............. .. .. .. ............. ............. ............ ............. .... 17
3.4 Signal Terminations and Unused Pins ................................................................... 17
3.5 FSB Frequency Select Signals (BSEL[1:0])............................................................ 17
3.6 FSB Signal Groups............................................................................................. 17
3.7 CMOS Signals ................................................................................................... 19
3.8 Maximum Ratings . ............................................................................................. 19
3.9 Processor DC Specifications ................................................................................ 19
4 Package Mechanical Specifications and Pin Information .......................................... 29
4.1 Processor Pinout and Pin List .............................................................................. 37
4.2 Alphabetical Signals Reference............................................................................ 55
5 Thermal Specifications and Design Considerations .................................................. 63
5.1 Thermal Specifications ....................................................................................... 65
5.1.1 Thermal Diode ....................................................................................... 65
5.1.2 Thermal Diode Offset.............................................................................. 66
5.1.3 Intel® Thermal Monitor........................................................................... 67
4Datasheet
Figures
1 Clock Control States .................................................................................................11
2 Illustration of Deep Sleep State VCC Static and Ripple Tolerances
for the Celeron M Processor (Deep Sleep State): VID=1.260 V .......................................22
3 Illustration of Active State VCC Static and Ripple Tolerances
for the Celeron M Processor ULV: VID=0.940 V ................................ .. .. .. .... .. .. ..............24
4 Illustration of Deep Sleep State VCC Static and Ripple Tolerances
for the Celeron M Processor ULV: VID=0.940 V ................................ .. .. .. .... .. .. ..............25
5 Active VCC and ICC Loadline for the Celeron M Processor:
Standard Voltage and Ultra Low Voltag e ..... .. .. .. .. ....................... ........................ ..........25
6 Deep Sleep VCC and ICC Loadline for Celeron M Processors:
Standard Voltage and Ultra Low Voltag e ..... .. .. .. .. ....................... ........................ ..........26
7 Micro-FCPGA Package Top and Bottom Isometric Views .................................................29
8 Micro-FCPGA Package - Top and Side Views .................................................................30
9 Micro-FCPGA Package - Bottom View...........................................................................31
10 Micro-FCBGA Package Top and Bottom Isometric Views .................................................33
11 Micro-FCBGA Packag e Top and Side Views .............. ... ..................................................34
12 Micro-FCBGA Packag e Bottom Vie w............ .. .. ............. ....................... ....................... ..36
13 The Coordinates of the Processor Pins As Viewed from the Top of the Package..................38
Tables
1 Voltage Identification Definition..................................................................................16
2 FSB Pin Groups ........................................................................................................18
3 Processor DC Absolute Maximum Ratings.....................................................................19
4 Voltage and Current Specifications..............................................................................20
5 Voltage Tolerances for the Celeron M Processor (Deep Sleep State).................................22
6 Voltage Tolerances for the Celeron M Processor ULV (Active State)............... ...................23
7 Voltage Tolerances for the Celeron M Processor ULV (Deep Sleep State) ..........................24
8 FSB Differential BCLK Specifications............................................................................26
9 AGTL+ Signal Group DC Specifications ........................................................................27
10 CMOS Signal Group DC Specifications..........................................................................27
11 Open Drain Signal Group DC Specifications .... ..............................................................28
12 Micro-FCPGA Package Dimensions ........... .. .................................................................32
13 Micro-FCPGA Package Dimensions ........... .. .................................................................35
14 Pin Listing by Pin Name.............................................................................................39
15 Pin Listing by Pin Number ..........................................................................................46
16 Signal Description........ ........... .. ........... .. .. .......... .. ... .......... .. .. ........... .. .. ........... .. ........55
17 Power Specifications for the Celeron M Processor ..........................................................64
18 Thermal Diode Interface............................................................................................66
19 Thermal Diode Specification....................................................................................... 66
Datasheet 5
Revision History
§
Revision Description Date
-001 Initial release July 2004
-002
Updates include:
• Document Title from “Intel® Celeron® M Processor Ultra Low
Voltage on 90 nm Process” to “Intel® Celeron® M Processor on
90 nm Process”
• Added Micro-FCPGA package information throughout Chapter 4
• Celeron® M Processor 360 and 350 DC and Thermal and Power
Specifications (Updated Table 4 and Table 17)
August 2004
-003
Updates include:
• Added resources to the Reference Table 1
• BSEL[1:] literature updated
• Celeron M processor 370 and 373 DC and Thermal and Power
Specifications (Updated Table 4 and Table 17)
• Execute Disable bit and Lead Free feature referenced
January 2005
-004 • Celeron M processor 383 DC and Thermal and P ower Specifications
(Updated Table Table 4 and Table 17)April 2005
-005 • Added Celeron M processor 380 specifications July 2005
-006
• Updated Celeron M processor 370, 360J, 350J and Celeron M
processor UL V 383, 373 specifications for optimized VID (T Table 4
and Table 17)
• Updated Celeron M processor ULV 383, 373 TDP specification
(Table 17)
July 2005
-007 • Added Celeron M processor 390 specifications January 2006
-008 • Updated Celeron M 390 Thermal Specifications January 2007
6Datasheet
Datasheet 7
Introduction
1 Introduction
The Intel® Celeron® M processor based on 90 nm process technology is a high-
performance, low-power mobile processor with several enhancements over previous
mobile Celeron processors.
Throughout this document, the term Celeron M processor signifies Intel Celeron M
processor based on 90 nm technology.
This document contains specification for the Celeron M processor 390, 380, 370, 360J,
360, 350J, 350Δ and the Celeron M processor Ultra Low Vo ltage 383, 373, 353Δ.
Note: ΔIntel processor numbers are not a measure of performance. Processor numbers
differentiate features within each processor family, not across different processor
families. See www.intel.com/products/processor_number for details.
The following list provides some of the key features on this processor:
• Manufactured on Intel’s advanced 90 nanometer process technology with copper
interconnect.
• Supports Intel Architecture with Dynamic Execution
• On-die, primary 32-KB instruction cache and 32-KB write-back data cache
• On-die 1-MB (512-KB for Celeron M processor Ultra Low Voltage 373 and 353)
second level cache with Advanced Transfer Cache Architecture, 8-way set
associativity and ECC (Error Correcting Code) Support.
• Data Prefetch Logic
• Streaming SIMD extensions 2 (SSE2)
• 400-MHz, source-synchronous front side bus (FSB)
• Micro-FCPGA and Micro-FCBGA (ULV parts available only in Micro-FCBGA)
packaging technologies (including lead free technology for the Micro-FCBGA
package for Celeron M processors 390, 380, 370, 383, 373, and 353).
• Execute Disable Bit support for enhanced security (available on processors with
CPU Signature=06D8h and recommended for implementation on Intel® 915/910
Express Chipset-based platforms only)
The Celeron M processor maintains support for MMX™ technology and Internet
Streaming SIMD instructions and full compatibility with IA-32 software. The on-die,
32-KB Level 1 instruction and data caches and the 1-MB (512-KB for Celeron M
processor Ultra Low Voltage 373 and 35 3) Level 2 cache with advanced transfer cache
architecture enable significant performance improvement over existing mobile
processors. The processor’s data prefetch logic speculatively fetches data to the L2
cache before an L1 cache requests occurs, resulting in redu ced bus cycle penalties and
improved performance.
The streaming SIMD extensions 2 (SSE2) enable break-through levels of performance
in multimedia applications including 3-D graphics, video decoding/encoding, and
speech recognition. The new packed double-precision floating-point instructions
enhance performance for applications that require greater range and precision,
including scientific and engineering applications and adv anced 3-D geometry
techniques, such as ray tracing.
The Celeron M processor’s 400-MHz FSB utilizes a split-transaction, deferred reply
protocol. The 400-MHz FSB uses source-synchronous transfer (SST) of address and
data to improve performance by transferring data four times per bus clock (4X data
Introduction
8Datasheet
transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver
addresses two times per bus clock and is referred to as a “double-clocked” or 2X
address bus. W orking together, the 4X data bus and 2X address bus provide a data bus
bandwidth of up to 3.2 GB/second. The FSB uses Advanced Gunning Transceiver Logic
(AGTL+) signalling technology, a variant of (GTL+) signaling technology with low power
enhancements.
The Celeron M processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro-
FCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package
technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, zero
insertion force (ZIF) socket, which is referred to as the mPGA479M socket.
1.1 Terminology
1.2 References
Material and concepts available in the following documents may be beneficial when
reading this document.
Term Definition
#
A “#” symbol after a signal name refers to an active low signal, indicating a
signal is in the active state when driven to a low level. For example, when
RESET# is low, a reset has been requested. Conversely, when NMI is high,
a nonmaskable interrupt has occurred. In the case of signals where the
name does not imply an active state but describes part of a binary
sequence (such as address or data), the “#” symbol implies th at the s ignal
is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#
= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
XXXX means that the specification or value is yet to be determined.
Front Side Bus
(FSB) Refers to the interface between the processor and system core logic (also
known as the chipset components).
Document Document Location1
Intel® Celeron® M Processor Specification Update http://www.intel.com/
design/mobile/specupdt/
300303.htm
Mobile Intel® 915PM/GM/GMS and 910GML Express Chipset
Datasheet
http://www.intel.com/
design/mobile/datashts/
305264.htm
Mobile Intel® 915PM/GM/GMS and 910GML Express Chipset
Specification Update
http://www.intel.com/
design/mobile/specupdt/
307167.htm
Intel® I/O Controller Hub 6 (ICH6) Family Datasheet http://www.intel.com/
design/chipsets/datashts/
301473.htm
Intel® I/O Controller Hub 6 (ICH6) Family Specification Update http://www.intel.com/
design/chipsets/specupdt/
301474.htm
Intel® 855PM Chipset Memory Controller Hub (MCH) Datasheet http://www.intel.com/
design/chipsets/datashts/
252613.htm
Datasheet 9
Introduction
§
Intel® 855PM Chipset MCH DDR 333/200/266 MHz Specification
Update
http://www.intel.com/
design/chipsets/specupdt/
253488.htm
Intel® 855GM/GME Chipset Graphics and Memory Controller Hub
(GMCH) Datasheet
http://www.intel.com/
design/chipsets/datashts/
252615.htm
Intel® 855GM/GME Chipset Graphics and Memory Controller Hub
(GMCH) Specification Update
http://www.intel.com/
design/chipsets/specupdt/
253572.htm
Intel® 82801DBM I/O Controll er Hub 4 Mobile ( ICH4-M) Datashe et http://www.intel.com/
design/mobile/datashts/
252337.htm
Intel® 82801DBM I/O Controll er Hub 4 Mobile (ICH4-M) Datasheet
Specification Update
http://www.intel.com/
design/chipsets/specupdt/
252663.htm
IA-32 Intel® Architecture Software Developer's Manuals
http://www.intel.com/
design/pentium4/manuals/
index_new.htm
Volume 1: Basic Architecture
Volume 2A: Inst ruction Set Reference, A- M
Volume 2B: Instruction Set Reference, N-Z
Volume 3A: System Programming Guide
Volume 3B: System Programming Guide
Document Document Location1
Introduction
10 Datasheet
Datasheet 11
Low Power Features
2 Low Power Features
2.1 Clock Control and Low Power States
The Celeron M processor supports the AutoHALT Power-Down, Stop Grant, Sleep, Deep
Sleep states for optimal power management. See Figure 1 for a visual representation of
the processor low-power states.
2.1.1 Normal State
This is the normal operating state for the processor.
2.1.2 AutoHALT Power-Down State
AutoHALT Power-Down is a low-power state entered when the processor executes the
HALT instruction. The processor will tr ansition to the Normal state upon the occurrence
of SMI#,INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause
the processor to immediately initialize itself.
The system can generate a STPCLK# while the processor is in the AutoHALT Power-
Down state. When the system deasserts the STPCLK# interrupt, the processor will
return execution to the HAL T state. While in AutoHALT P ower-Down state, the processor
will process bus snoops and interrupts.
2.1.3 Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entere d 20
bus clocks after the response phase of the processor issued Stop-Grant Acknowledge
special bus cycle.
Figure 1. Clock Control States
snoop
occurs
Stop
Grant
Normal Sleep
HALT/
Grant
Snoop
Auto Halt Deep
Sleep
STPCLK# asserted SLP# asserted
SLP# deasserted
ST P C LK# deasse rted
snoop
serviced
HLT
instruction
snoop
serviced snoop
occurs
DPSLP#
de-asserted DPSLP#
asserted
STPCLK#
asserted
STPCLK#
deasserted
halt
break
V0001-04
Halt bre ak - A20M#, INIT #, INTR, N MI, PREQ#, RESET# , SMI#, o r APIC interrupt
Low Power Features
12 Datasheet
Since the AGTL+ signal pins receive power from the FSB, these pins should not be
driven (allowing the level to return to VCCP) for minimum power drawn by the
termination resistors in this state. In addition, all other input pins on the FSB should be
driven to the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. A transition back to the Normal state will occur with the
deassertion of the STPCLK# signal. When re-entering the Stop-Grant state from the
Sleep state, STPCLK# should be deasserted ten or more bus clocks after the
deassertion of SLP#.
A transition to the HALT/Grant Snoop state will occur when the processor detects a
snoop on the FSB (see Section 2.1.4). A transition to the Sleep state (see
Section 2.1.5) will occur with the assertion of the SLP# signal.
While in the Stop-Grant state, SMI#, INIT# and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal State. Only one
occurrence of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process snoops on the FSB, and it will
latch interrupts delivered on the FSB.
The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be
asserted if there is any pending interrupt latched within the processor. Pending
interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of
PBE#. Assertion of PBE# indicates to system logic that it should return the processor to
the Normal state.
2.1.4 HALT/Grant Snoop State
The processor will respond to snoop or interrupt transactions on the FSB while in Stop-
Grant state or in AutoHALT Power-Down state. Durin g a snoop or interrupt transaction,
the processor enters the HALT/Grant Snoop state. The processor will stay in this state
until the snoop on the FSB has been serviced (whether by the processor or another
agent on the FSB) or the interrupt has been latched. After the snoop is serviced or the
interrupt is latched, the processor will return to the Stop-Grant state or AutoHALT
Power-Down state, as appropriate.
2.1.5 Sleep State
A low power state in which the processor maintains its context, maintains the phase-
locked loop (PLL), and has stopped all internal clocks. The Sleep state can be entered
only from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the
Sleep state upon the assertion of the SLP# signal. The SLP# pin should only be
asserted when the processor is in the Stop Grant state. SLP# assertions while the
processor is not in the Stop-Grant state is out of specification and may result in
unapproved operation.
Snoop events that occur while in Sleep State or during a transition into or out of Sleep
state will cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals (with the exception of
SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep
state. Any transition on an input signal before the processor has returned to Stop-Grant
state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as
specified in the RESET# pin specification, then the processor will reset itself, ignoring
the transition through Stop-Gr ant State. If RESET# is driven activ e while the processor
Datasheet 13
Low Power Features
is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately
after RESET# is asserted to ensure the processor correctly executes the reset
sequence.
While in the Sleep state, the processor is capable of entering an even lower power
state, the Deep Sleep state by asserting the DPSLP# pin. (See Section 2.1.6.) While
the processor is in the Sleep state, the SLP# pin must be deasserted if another
asynchronous FSB event needs to occur.
2.1.6 Deep Sleep State
Deep Sleep state is a very low power state the processor can enter while maintaining
context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep
state. BCLK may be stopped during the Deep Sleep state for additional platform level
power savings. BCLK stop/restart timings on 855PM chipset family based platforms
with compatible clock generator chips are as follows:
• Deep Sleep entry - DPSLP# and CPU_STP# are asserted simultaneously. The clock
chip will stop/tristate BCLK within two BCLKs +/- a few nanoseconds.
• Deep Sleep exit - DPSLP# and CPU_STP# are deasserted simultaneously. The clock
chip will drive BCLK to differential DC levels within 2-3 ns and starts toggling BCLK
2-6 BCLK periods later.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted
after DPSLP# deassertion as described above. A period of 30 microseconds (to allow for
PLL stabilization) must occur before the processor can be considered to be in the Sleep
State. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-
Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop
transactions or latching interrupt signals. No transitions of signals are allowed on the
FSB while the processor is in Deep Sleep state. Any transition on an input signal before
the processor has returned to Stop-Grant state will result in unpredictable behavior.
When the processor is in Deep Sleep state, it will not respond to interrupts or snoop
transactions.
2.2 FSB Low Power Enhancements
The Celeron M processor incorporates the FSB low power enhancements:
• Dynamic FSB Power Down
• BPRI# control for address and control input buffers
• Dynamic On Die Termination disabling
• Low VCCP (I/O termination voltage)
The Celeron M processor incorporates the DPWR# signal that controls the data bus
input buffers on the processor. The DPWR# sig nal disables the buffers when not used
and activates them only when data bus activity occurs, resulting in significant power
savings with no performance impact. BPRI# control also allows the processor address
and control input buffers to be turned off wh en the BPRI# signal is inactiv e. The on-die
termination on the processor FSB buffers is disabled when the signals are driven low,
resulting in additional power savings. The low I/O termination voltage is on a dedicated
voltage plane independent of the core voltage, enabling low I/O switching power at all
times.
Low Power Features
14 Datasheet
2.3 Processor Power Status Indicator (PSI#) Signal
The Celeron M processor incorporates the PSI# signal that is asserted when the
processor is in a low power (Deep Sleep) state. This signal is asserted upon Deep Sleep
entry and deasserted upon exit. PSI# can be used to improve the light load efficiency
of the voltage regulator, resulting in platform power savings and extended battery life.
§
Datasheet 15
Electrical Specifications
3 Electrical Specifications
3.1 Power and Ground Pins
For clean, on-chip power distribution, the Celeron M processor has a large number of
VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power
planes while all VSS pins must be connected to system ground planes. Use of multiple
power and ground planes is recommended to reduce I*R drop. Please refer to the
platform design guides for more details. The processor VCC pins must be supplied the
voltage determined by the VID (Voltage ID) pins.
3.1.1 FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the Celeron M processor core
frequency is a multiple of the BCLK[1:0] frequency. The Celeron M processor uses a
differential clocking implementation.
3.2 Voltage Identification and Power Sequencing
The Celeron M processor uses six voltage identification pins, VID[5:0], to support
automatic selection of power supply voltages. The VID pins for Celeron M processor are
CMOS outputs driven by the processor VID circuitry. Table 1 specifies the voltage level
corresponding to the state of VID[5:0].
Electrical Specifications
16 Datasheet
Table 1. Voltage Identification Defi nition
VID Vcc V VID Vcc V
543 2 1 0 5432 1 0
000 0 0 01.7081000 0 01.196
000 0 0 11.6921000 0 11.180
000 0 1 01.6761000 1 01.164
000 0 1 11.6601000 1 11.148
000 1 0 01.6441001 0 01.132
000 1 0 11.6281001 0 11.116
000 1 1 01.6121001 1 01.100
000 1 1 11.5961001 1 11.084
001 0 0 01.5801010 0 01.068
001 0 0 11.5641010 0 11.052
001 0 1 01.5481010 1 01.036
001 0 1 11.5321010 1 11.020
001 1 0 01.5161011 0 01.004
001 1 0 11.5001011 0 10.988
001 1 1 01.4841011 1 00.972
001 1 1 11.4681011 1 10.956
010 0 0 01.4521100 0 00.940
010 0 0 11.4361100 0 10.924
010 0 1 01.4201100 1 00.908
010 0 1 11.4041100 1 10.892
010 1 0 01.3881101 0 00.876
010 1 0 11.3721101 0 10.860
010 1 1 01.3561101 1 00.844
010 1 1 11.3401101 1 10.828
011 0 0 01.3241110 0 00.812
011 0 0 11.3081110 0 10.796
011 0 1 01.2921110 1 00.780
011 0 1 11.2761110 1 10.764
011 1 0 01.2601111 0 00.748
011 1 0 11.2441111 0 10.732
011 1 1 01.2281111 1 00.716
011 1 1 11.2121111 1 10.700
Datasheet 17
Electrical Specifications
3.3 Catastrophic Thermal Protection
The Celeron M processor supports the THERMTRIP# signal for catastrophic thermal
protection. An external thermal sensor should also be used to protect the processor
and the system against excessive temperatures. Even with the activ ation of
THERMTRIP#, which halts all processor internal clocks and activity, leakage current can
be high enough such that the processor cannot be protected in all conditions without
the removal of power to the processor. If the external thermal sensor detects a
catastrophic processor temperature of 125°C (maximum), or if the THERMTRIP# signal
is asserted, the VCC supply to the processor must be turned off within 500 ms to
prevent permanent silicon damage due to thermal runaway of the processor.
3.4 Signal Terminations and Unused Pins
All RSVD (RESERVED) pins must remain unconnected. Connection of these pin s to VCC,
VSS, or to any other signal (including each other) can result in component malfunction
or incompatibility with future Celeron M processors. See Section 4.2 for a pin listing of
the processor and the location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if
AGTL+ termination is provided on the processor silicon. Unused active high inputs
should be connected through a resistor to ground (VSS). Unused outputs can be left
unconnected.
The TEST1 and TEST2 pins must have a stuffing option connection to VSS separ ately via
1-kΩ, pull-down resistors.
3.5 FSB Frequency Select Signals (BSEL[1:0])
The BSEL[1:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). These signals should be connected to the clock chip and Intel 915PM/GM/
GMS and 910GML Express Chipset on the platform. These signals must be left
unconnected on platforms designed with the Celeron M processor and the Intel 852/
855 chipset families.
3.6 FSB Signal Groups
In order to simplify the following discussion, the FSB signals have been combined into
groups by buffer type. AGTL+ input signals have differential input buffers, which use
GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+
Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when
driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 2 ide n tifies which signals are common clock, source synchronous,
and asynchronous.
Electrical Specifications
18 Datasheet
NOTES:
1. BPM[2:0}# and PRDY# are AGTL+ output only signals.
2. In processor systems where there is no debug port implemented on the system board, these signals are
used to support a debug port interposer. In systems with the debug port implemented on the system
board, these signals are no connects.
Table 2. FSB Pin Groups
Signal Group Type Signals
AGTL+ Common Clock Input Synchronous to
BCLK[1:0] BPRI#, DEFER#, DPWR#, PREQ#, RESET#,
RS[2:0]#, TRDY#
AGTL+ Common Clock I/O Synchronous to
BCLK[1:0] ADS#, BNR#, BPM[3:0]#, BR0#, DBSY#, DRDY#,
HIT#, HITM#, LOCK#, PRDY#
AGTL+ Source Synchronous I/O Synchronous to
assoc. strobe
AGTL+ Strobes Synchronous to
BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
CMOS Input Asynchronous A20M#, DPSLP#, IGNNE#, INIT#, LINT0/INTR,
LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK#
Open Drain Output Asynchronous FERR#, IERR#, PROCHOT#, THERMTRIP#
CMOS Output Asynchronous PSI#, VID[5:0], BSEL[1:0]
CMOS Input Synchronous to TCK TCK, TDI, TMS, TRST#
Open Drain Output Synchronous to TCK TDO
FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]2
Power/Other COMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1,
THERMDA, THERMDC, VCC, VCCA[3:0], VCCP,
VCCQ[1:0], VCC_SENSE, VSS, VSS_SENSE
Signals Associated Strobe
REQ[4:0]#,
A[16:3]# ADSTB[0]#
A[31:17]# ADSTB[1]#
D[15:0]#, DINV0# DSTBP0#, DSTBN0#
D[31:16]#, DINV1# DSTBP1#, DSTBN1#
D[47:32]#, DINV2# DSTBP2#, DSTBN2#
D[63:48]#, DINV3# DSTBP3#, DSTBN3#
Datasheet 19
Electrical Specifications
3.7 CMOS Signals
CMOS input signals are shown in Table 2. Legacy output FERR#, IERR# and other non-
AGTL+ signals (THERMTRIP# and PROCHOT#) utilize open drain output buffers. These
signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,
all of the CMOS signals are required to be asserted for at least three BCLKs in order for
the processor to reco gnize them. See Section 3.9 for the CMOS signal group DC
specifications.
3.8 Maximum Ratings
Table 3 lists the processor’s maximum environmental stress ratings. The processor
should not receive a clock while subjected to these conditions. Functional operating
parameters are listed in the AC and DC tables. Extended exposure to the maximum
ratings may affect device reliability. Furthermore, although the processor contains
protective circuitry to resist damage from electro static discharge (ESD), one should
always take precautions to avoid high static voltages or electric fields.
NOTES:
1. This rating applies to any processor pin.
2. Contact Intel for storage requirements in excess of one year.
3.9 Processor DC Specifications
The processor DC specifications in this section are defined at the processor
core (pads) unless noted otherwise. See Table 2 for pin signal definitions and
signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group.
The DC specifications for these signals are listed in Table 9. DC specifications for the
CMOS group are listed in Table 10.
Table 4 through Table 10 list the DC specifications for the Celeron M processor and are
valid only while meeting specifications for junction temperature, clock frequency, and
input voltages. Active mode load line specifications apply in all states except in the
Deep Sleep state. VCC,BOOT is the default voltage driven by the voltage regulator at
power up in order to set the VID values. Unless specified otherwise, all specifications
for the Celeron M processor are at Tjunction = 100°C. Care should be taken to read all
notes associated with each parameter.
Table 3. Processor DC Absolute Maximum Ratings
Symbol Parameter Min Max Unit Notes
TSTORAGE Processor Storage Temperature -40 85 °C 2
VCC Any Processor Supply Voltage with Respect to VSS -0.3 1.6 V 1
VinAGTL+ AGTL+ Buffer DC Input Voltage with Respect to VSS -0.1 1.6 V 1, 2
VinAsynch_CMOS CMOS Buffer DC Input Voltage with Respect to VSS -0.1 1.6 V 1, 2
Electrical Specifications
20 Datasheet
Table 4. Voltage and Current Specifications (Sheet 1 of 2)
Symbol Parameter Min Typ Max Unit Notes
VCC1 Intel® Celeron® M Processor 360, 350 Core
VCC 1.260 V 1,2,9
VCC2 Celeron M Processor 390, 3 80, 370, 360J, 350J
Core VCC 1.004 1.292 V 2,9,11
VCC3 Celeron M Processor Ultra Low Voltage 383,
373 Core VCC 0.876 0.956 V 2,9,11,
12
VCCULV Celeron M Processor Ultra Low Voltage 353
Core VCC 0.940 V 1,2,9
VCC,BOOT Default VCC Voltage for Initial Power-up 1.14 1.20 1.26 V 2
VCCP AGTL+ Termination Voltage 0.997 1.05 1.102 V 2
VCCA PLL Supply Voltages 1.71
1.425
1.8
1.5
1.89
1.575 V2,10
ICCDES ICC for Celeron M processor Recommended
Design Target 25 A 5
ICC
ICC for Celeron M processor 390, 380, 370,
360J, 350J & VCC2 21.0 A 3,9,11
ICC for Celeron M processor 360, 350 &1.260 V 21.0 A 3,9
ICCULV
ICC for Celeron M processor Ultra Low Voltage
383, 373 & VCC3 7.0 A 3,9,11,
12
ICC for Celeron M processor Ultra Low Voltage
353 & 0.940 V 7.0 A 3,9
IAH,
ISGNT
ICC Auto-Halt & Stop-Grant for Celeron M
Processor 390, 380, 370, 360J, 350J & VCC2 16.4 A 4,9,11
ICC Auto-Halt & Stop-Grant for Celeron M
Processor 360, 350 & 1.260 V 16.4 A 4,9
IAHULV,
ISGNTULV
ICC Auto-Halt & Stop-Grant for Celeron M
processor Ultra Low Voltage 383, 373 & VCC3 3.4 A 4,9,11,
12
ICC Auto-Halt & Stop-Grant for Celeron M
processor Ultra Low Voltage 353 & 0.940 V 3.4 A 4,9
ISLP
ICC Sleep for Celeron M processor 390, 380,
370, 360J, 350J & VCC2 16.1 A 4,9,11
ICC Sleep for Celeron M processor 360, 350 &
1.260 V 16.1 A 4,9
ISLPULV
ICC Sleep for Celeron M processor Ultra Low
Voltage 383, 373 & VCC3 3.3 A 4,9,11,
12
ICC Sleep for Celeron M processor Ultra Low
Voltage 353 & 0.940 V 3.3 A 4,9
IDSLP
ICC Deep Sleep for Celeron M processor 390,
380, 370, 360J, 350J & VCC2 15.5 A 4,9,11
ICC Deep Sleep for Celeron M processor 360,
350 & 1.260 V 15.5 A 4,9
Datasheet 21
Electrical Specifications
NOTES:
1. The typical values shown are the VID encoded voltages. Static and ripple tolerances (for minimum and
maximum voltages) are defined in the loadline t ables i.e., Table 5 through Table 7.
2. The voltage specifications are assumed to be measured at a via on the motherboard’s opposite side of the
processor’s socket (or BGA) ball with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe
capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be
less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.
3. Specified at VCC,STATIC (nominal) under maximum signal loading conditions.
4. Specified at the VID voltage.
5. The ICCDES(max) specification comprehends future processor HFM frequencies. Platforms should be
designed to this specification.
6. Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
7. Measured at the bulk capacitors on the motherboard.
8. Adherence to loadline specification for the Celeron M processor is required to ensure reliable processor
operation.
9. Intel processor numbers are not a measure of performance. Processor numbers differentiate features
within each processor family, not across different processor families. See www.intel.com/products/
processor_number for details.
10. The Celeron M processor will support VCCA supply voltage o f either 1.8 V ±5% o r 1.5 V ±5%. Either on e of
these voltages can be us ed on the platform.
11. These are VID values. Individual processor VID values may be calibrated during manufacturing such that
two devices at the same speed may have different VID settings. Actual voltage supplied to the processor
should be as specified in the load lines in Figure 5 and Figure 6. Adherence to load line specifications is
required to ensure reliable processor operation.
12. For 350J and 360J, CPU signature = 06D8h.
IDSLPULV
ICC Deep Sleep for Celeron M processor Ultra
Low Voltage 383, 373 & VCC3 3.0 A 4,9,11,
12
ICC Deep Sleep for Celeron M processor Ultra
Low Voltage 353 & 0.940 V 3.0 A 4,9
dICC/DT VCC power supply current slew rate 0.5 A/ns 6, 7
ICCA ICC for VCCA Supply 120 mA
ICCP ICC for VCCP supply 2.5 A
Table 4. Voltage and Current Sp ecifications (Sheet 2 of 2)
Symbol Parameter Min Typ Max Unit Notes
Electrical Specifications
22 Datasheet
Table 5. Voltage Tolerances for the Celeron M Processor (Deep Sleep State)
Mode
VID = 1.260 V, Offset = 1.2%
ICC, A VCC, V Static Ripple
Min Max Min Max
Deep Sleep
0.0 1.245 1.226 1.264 1.216 1.274
1.0 1.242 1.223 1.261 1.213 1.271
2.1 1.239 1.220 1.258 1.210 1.268
3.1 1.236 1.217 1.254 1.207 1.264
4.1 1.232 1.214 1.251 1.204 1.261
5.2 1.229 1.210 1.248 1.200 1.258
6.2 1.226 1.207 1.245 1.197 1.255
7.2 1.223 1.204 1.242 1.194 1.252
8.3 1.220 1.201 1.239 1.191 1.249
9.3 1.217 1.198 1.236 1.188 1.246
10.3 1.214 1.195 1.233 1.185 1.243
11.4 1.211 1.192 1.230 1.182 1.240
12.4 1.208 1.189 1.227 1.179 1.237
13.4 1.205 1.186 1.223 1.176 1.233
14.5 1.201 1.183 1.220 1.173 1.230
15.5 1.198 1.179 1.217 1.169 1.227
Figure 2. Illustration of Deep Sleep State VCC Static and Ripple Tolerances
for the Celeron M Processor (Deep Sleep State): VID=1.260 V
VID = 1. 260: Deep Sleep
1.245
1.160
1.180
1.200
1.220
1.240
1.260
1.280
0.0 2.0 4.0 6.0 8.0 10.0 12.0
STATIC Sta tic Min St at ic M ax R ipple M in R ipple M ax
Datasheet 23
Electrical Specifications
Table 6. Voltage Tolerances for th e Celeron M Processor ULV (Activ e State)
Mode
VID = 0.940 V, Offset=0%
ICC, A VCC, V Static Ripple
MinMaxMinMax
Active
0 0.940 0.926 0.954 0.916 0.964
0.3 0.939 0.925 0.953 0.915 0.963
0.5 0.938 0.924 0.953 0.914 0.963
0.8 0.938 0.924 0.952 0.914 0.962
1.0 0.937 0.923 0.951 0.913 0.961
1.3 0.936 0.922 0.950 0.912 0.960
1.6 0.935 0.921 0.949 0.911 0.959
1.8 0.935 0.920 0.949 0.910 0.959
2.1 0.934 0.920 0.948 0.910 0.958
2.3 0.933 0.919 0.947 0.909 0.957
2.6 0.932 0.918 0.946 0.908 0.956
2.9 0.931 0.917 0.946 0.907 0.956
3.1 0.931 0.917 0.945 0.907 0.955
3.4 0.930 0.916 0.944 0.906 0.954
3.6 0.929 0.915 0.943 0.905 0.953
3.9 0.928 0.914 0.942 0.904 0.952
4.1 0.928 0.913 0.942 0.903 0.952
4.4 0.927 0.913 0.941 0.903 0.951
4.7 0.926 0.912 0.940 0.902 0.950
4.9 0.925 0.911 0.939 0.901 0.949
5.2 0.924 0.910 0.939 0.900 0.949
5.4 0.924 0.910 0.938 0.900 0.948
5.7 0.923 0.909 0.937 0.899 0.947
6.0 0.922 0.908 0.936 0.898 0.946
6.2 0.921 0.907 0.935 0.897 0.945
6.5 0.921 0.906 0.935 0.896 0.945
6.7 0.920 0.906 0.934 0.896 0.944
7.0 0.919 0.905 0.933 0.895 0.943
Electrical Specifications
24 Datasheet
Figure 3. Illustration of Active State VCC Static and Ripple Tolerances
for the Celeron M Processor ULV: VID=0.940 V
VID = 0.940: Active
0.940
0.890
0.900
0.910
0.920
0.930
0.940
0.950
0.960
0.970
0123456
ICC, A
VCC, V
STATIC Static Min Static Max Ripple Min Ripple Max
Table 7. Voltage Tolerances for the Celero n M Processor ULV (Deep Sleep State)
Mode
VID = 0.940 V, Offset=0%
ICC, A VCC, V Static Ripple
Min Max Min Max
Active
0 0.929 0.915 0.943 0.905 0.953
0.2 0.928 0.914 0.942 0.904 0.952
0.4 0.928 0.913 0.942 0.903 0.952
0.6 0.927 0.913 0.941 0.903 0.951
0.8 0.926 0.912 0.940 0.902 0.950
1.0 0.926 0.912 0.940 0.902 0.950
1.2 0.925 0.911 0.939 0.901 0.949
1.4 0.925 0.910 0.939 0.900 0.949
1.6 0.924 0.910 0.938 0.900 0.948
1.8 0.923 0.909 0.937 0.899 0.947
2.0 0.923 0.909 0.937 0.899 0.947
2.2 0.922 0.908 0.936 0.898 0.946
2.4 0.922 0.907 0.936 0.897 0.946
2.6 0.921 0.907 0.935 0.897 0.945
2.8 0.920 0.906 0.934 0.896 0.944
3.0 0.920 0.906 0.934 0.896 0.944
Datasheet 25
Electrical Specifications
Figure 4. Illustration of Deep Sleep State VCC Static and Ripp le Tolerances
for the Celeron M Processor ULV: VID=0.940 V
Figure 5. Active VCC and ICC Loadline for the Celeron M Processor:
Standard Voltage and Ultra Low Voltage
VID = 0.940V: Dee p Sle e p
0.929
0.890
0.900
0.910
0.920
0.930
0.940
0.950
0.960
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
I cc, A
Vcc, V
STATIC St atic M in St atic M a x Rippl e M in R ipple M ax
ICC max
VCC [V]
Slope= -3.0 mV/A
+/-1.5% from No minal = V R Error
10mV= RIPPLE
ICC
[A]
0
VCC, DC Max
VCC Max
VCC Nom
VCC, DC Min
VCC Min
Electrical Specifications
26 Datasheet
NOTES:
1. Unless other wise noted, all sp ecification s in this table apply to all processor frequencies.
2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of
BCLK1.
3. Threshold R egion is defined as a region entered about the crossing voltage in which the differential receiver
switches. It includes input threshol d hyst eresis.
4. For Vin between 0 V and VIH.
5. Cpad includes die capacitance only. No package parasitics are included.
6. ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2.
Figure 6. Deep Sleep VCC and ICC Loadline for Celeron M Processors:
Standard Voltage and Ultra Low Voltage
Table 8. FSB Differential BCLK Specifications
Symbol Parameter Min Typ Max Unit Notes1
VIH Input High Voltage 0.660 0.710 0.850 V
VIL Input Low Voltage 0 V
VCROSS Crossing Voltage 0.250.350.55V2
ΔVCROSS Range of Crossing Points N/A N/A 0.140 V 6
VTH Threshold Region VCROSS - 0.100 VCROSS + 0.100 V 3
ILI Input Leakage Current ± 100 µA 4
Cpad Pad Capacitance 1.8 2.3 2.75 pF 5
ICC max
VCC [V]
Slope= -3.0 mV/A
Vcc nom - 1.2%
+/-1.5% from Nominal =VR Error
10mV= R IPPLE
ICC
[A]
0Deep Sleep
Datasheet 27
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
value.
3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
4. VIH and VOH may experience excursions above VCCP
. However, input signal drivers must comply with the
signal quality specifications in Chapter 3.
5. This is the pull-down driver resistance. Refer to processor I/O buffer models for I/V characteristics.
Measured at 0.31*VCCP
. RON (min) = 0.38*RTT, RON (typ) = 0.45*RTT, RON (max) = 0.52*RTT.
6. GTLREF should be generated from VCCP with a 1% tolerance resistor divider. The VCCP referred to in these
specifications is the instantaneous VCCP
.
7. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at
0.31*VCCP
. RTT is connected to VCCP on die. Refer to processor I/O buffer models for I/V characteristics.
8. Specified with on die RTT and RON are turned off.
9. Cpad includes die capacitance only. No package parasitics are included.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The VCCP referred to in these specifications refers to instantaneous VCCP
.
3. Measured at 0.1*VCCP
.
4. Measured at 0.9*VCCP
.
5. For Vin between 0 V and VCCP
. Measured when the driver is tristated.
6. Cpad includes die capacitance only. No package parasitics are included.
Table 9. AGTL+ Signal Group DC Specifications
Symbol Parameter Min Typ Max Unit Notes1
VCCP I/O Voltage 0.997 1.05 1.102 V
GTLREF Reference Voltage 2/3 VCCP - 2% 2/3 VCCP 2/3 VCCP + 2% V 6
VIH Input High Voltage GTLREF + 0.1 VCCP + 0.1 V 3,6
VIL Input Low Voltage -0.1 GTLREF - 0.1 V 2,4
VOH Output High Voltage VCCP 6
RTT Termination Resistance 47 55 63 Ω 7
RON Buffer On Resi stance 17.7 24.7 32.9 Ω5
ILI Input Leakage Current ±100 µA 8
Cpad Pad Capacitance 1.8 2.3 2.75 pF 9
Table 10. CMOS Signal Group DC Specifications
Symbol Parameter Min Typ Max Unit Notes1
VCCP I/O Voltage 0.997 1.05 1.102 V
VIH Input High Voltage 0.7*VCCP VCCP+0.1 V 2
VIL Input Low Voltage CMOS -0.1 0.3*VCCP V2, 3
VOH Output High Voltage 0.9*VCCP VCCP VCCP+0.1 V 2
VOL Output Low Voltage -0.1 0 0.1*VCCP V2
IOH Output High Current 1.49 4.08 mA 5
IOL Output Low Current 1.49 4.08 mA 4
ILI Input Leakage Current ±100 µA 6
Cpad Pad Capacitance 1.0 2.3 3.0 pF
Electrical Specifications
28 Datasheet
NOTES:
1. Unless other wise noted, all sp ecification s in this table apply to all processor frequencies.
2. Measured at 0.2 V.
3. VOH is determined by value of the external pull-up resistor to VCCP
.
4. For Vin between 0 V and VOH.
5. Cpad includes die capacitance only. No package parasitics are included.
§
Table 11. Open Drai n Signa l Group DC Specifications
Symbol Parameter Min Typ Max Unit Notes1
VOH Output H igh Voltage VCCP V3
VOL Output Low Voltage 0 0.20 V
IOL Output Low Current 16 50 mA 2
ILO Output Leakage Current ±200 µA 4
Cpad Pad Capacitance 1.7 2.3 3.0 pF 5
Datasheet 29
Package Mechanical Specifications and Pin Information
4 Package Mechanical
Specifications and Pin
Information
The Celeron M processor will be available in 478-pin, Micro-FCPGA and 479-ball, Micro-
FCBGA packages . Different views of the Micro-FCPGA package are shown in Figure 7
through Figure 9. Package dimensions are shown in Figure 7. Different views of the
Micro-FCBGA package are shown in Figure 7 throu gh Figure 9. P ackage dimensions are
shown in Table 8.
The Micro-FCBGA package may have capacitors placed in the area surrounding the die.
Because the die-side capacitors are electrically conductive, and only slightly shorter
than the die height, care should be taken to avoid contacting the capacitors with
electrically conductive materials. Doing so may short the capacitors, and possibly
damage the device or render it inactive. The use of an insulating material between the
capacitors and any thermal solution should be considered to prev ent capacitor shorting.
NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 12 for
details.
Figure 7. Micro-FCPGA Package Top and Bottom Isometric Views
TOP VIEW BOT TOM VIEW
LABEL
PACKAGE KEEPO UT
DIE
CAPACITOR AREA
Package Mechanical Specifications and Pin Information
30 Datasheet
NOTE: Die is centered on the Package. All dimensions in millimeters. Values shown for reference
only. Refer to Table 12 for details.
Figure 8. Micro-FCPGA Package - Top and Side Views
35 (E)
35 (D )
PIN A1 CORNER
E1
D1
A
1.25 MAX
(A3)
Ø0.32 (B)
478 places
2.03
±0.08
(A1)
A2
SUBSTRATE KEEPOUT ZONE
DO NO T CONTACT PACKAGE
IN SIDE T HIS L INE
7 (K1)
8 places
5 (K)
4 places
0.286
35 (E)
35 (D )
PIN A1 CORNER
E1
D1
A
1.25 MAX
(A3)
Ø0.32 (B)
478 places
2.03
±0.08
(A1)
A2
SUBSTRATE KEEPOUT ZONE
DO NO T CONTACT PACKAGE
IN SIDE T HIS L INE
7 (K1)
8 places
5 (K)
4 places
0.286 0.286
Datasheet 31
Package Mechanical Specifications and Pin Information
NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 12 for
details.
Figure 9. Micro-FCPGA Package - Bottom View
1 2
3
4 6 8 10 12 14 16 18 20 22 24 26
5 7 9 11 13 15 17 19 21 23 25
A
B C
E
D
F G
H J
K L
M N
P R
T U
V W
Y AA
AB AC
AD AE
AF
25X 1.27
(e)
25X 1.27
(e)
14 (K3)
14 (K3)
Package Mechanical Specifications and Pin Information
32 Datasheet
NOTES:
1. Over all height with socket is based on design dimensions of the Micro-FCPGA package with
no thermal solution attached. Values are based on design specifications and tolerances.
This dimension is subject to change based on socket design, OEM motherboard design or
OEM SMT process.
Table 12. Micro-FCPGA Package Dimensions
Symbol Parameter Min Max Unit
A Overall height, top of the die to package seating plane 1.88 2.02 mm
–Overall height, top of die to PCB surface, including
socket (Refer to Note 1) 4.74 5.16 mm
A1 Pin length 1.95 2.11 mm
A2 Die height 0.820 mm
A3 Pin-side capacitor height – 1.25 mm
B Pin diameter 0.28 0.36 mm
D Package substrate length 34.9 35.1 mm
E Package substrate width 34.9 35.1 mm
D1 Die length 12.54 mm
E1 Die width 6.99 mm
ePin pitch 1.27 mm
K Package edge keep-out 5 mm
K1 Package corner keep-out 7 mm
K3 Pin-side capacitor boundary 14 mm
N Pin count 478 each
Pdie Allowable pressure on the die for thermal solution - 689 kPa
WPackage weight 4.5 g
Package surface flatness 0.286 mm
Datasheet 33
Package Mechanical Specifications and Pin Information
Figure 10. Micro-FCBGA Package Top and Bottom Isometric Views
TOP VIEW BOTTOM VIEW
LABEL DIE
PACKAGE KEEPOUT
CAPACITOR AREA
Package Mechanical Specifications and Pin Information
34 Datasheet
NOTE: Die is centered on the Package. All dimensions in millimeters. Values shown for reference
only. Refer to Table 13 for details.
Figure 11. Micro-FCBGA Package Top and Side Views
35 (E)
35 (D)
PIN A1 CORNER
E1
D1
A
Ø0.78 (b)
479 places
K2
SUBSTRATE KEEPOUT ZONE
DO NOT CONTACT PACKAGE
INS IDE T HIS LI NE
7 (K1)
8 places
5 (K)
4 places A2
0.20
Datasheet 35
Package Mechanical Specifications and Pin Information
NOTES:
1. Overall height as delivered. Values are based on design specifications and tolerances. This
dimensi o n is su b ject to change based on OEM motherboard design or OEM SMT process
Table 13. Micro-FCPGA Package Dimensions
Symbol Parameter Min Max Unit
A Overall height, as delivered (Refer to Note 1) 2.60 2.85 mm
A2 Die height 0.82 mm
b Ball diameter 0.78 mm
D Package substrate length 34.9 35.1 mm
E Package substrate width 34.9 35.1 mm
D1 Die length 12.54 mm
E1 Die width 6.99 mm
eBall pitch 1.27 mm
K Package edge keep-out 5 mm
K1 Package corner keep-out 7 mm
K2 Die-side capacitor height – 0.7 mm
S Package edge to first ball center 1.625 mm
N Ball count 479 each
– Solder ball coplanarity 0.2 mm
Pdie Allowable pressure on the die for thermal solution – 689 kPa
WPackage weight 4.5 g
Package Mechanical Specifications and Pin Information
36 Datasheet
NOTE: All dimensio ns in millim eters. Values shown for reference only. Refer to Table 13 for
details.
Figure 12. Micro-FCBGA Package Bottom View
1 2 3
4 6 8 10 12 14 16 18 20 22 24 26
5 7 9 11 13 15 17 19 21 23 25
A
B C
E
D
F G
H J
K L
M N
P R
T U
V W
Y AA
AB AC
AD AE
AF
25X 1.27
(e)
25X 1. 27
(e)
1.625 (S)
4 places
1.625 (S)
4 places
Package Mechanical Specifications and Pin Information
38 Datasheet
Figure 13. The Coordinates of the Processor Pins As Viewed from the Top of the Package
1234567891011121314151617181920212223242526
IGNNE# IERR# VSS SLP# DBR# VSS BPM[2]# PRDY# VSS TDO TCK VSS ITP_CLK
[1] ITP_CLK
[0] VSS THER
MDC D[0]# VSS D[6]# D[2]# VSS D[4]# D[1]# VSS
VSS SMI# INIT# VSS DPSLP# BPM
[1]# VSS PREQ# RESET# VSS TRST# BCLK1 BCLK0 VSS PROC
HOT # THER
MDA VSS D[7]# D[3]# VSS D[13]# D[9]# VSS D[5]#
VSS A20M# RSVD VSS TEST1 STP
CLK# VSS BPM
[0]# BPM
[3]# VSS TMS TDI VSS BSEL[1] VSS BSEL[0] THERM
TRIP# VSS DPWR# D[8]# VSS DSTBP
[0]# DSTBN
[0]# VSS D[15]# D[12]#
LINT0 VSS FERR# LINT1 VSS VCC VSS VCC VSS VCCP VSS VCCP VSS VCCP VSS VCCP VSS VCC VSS VCC VSS VCC VSS D[10]# DINV
[0]# VSS
PSI# VID[0] PWR
GOOD VCC VSS VCC VSS VCC VSS VCCP VSS VCCP VSS VCCP VSS VCC VSS VCC VSS VCC VSS D[14]# D[11]# VSS RSVD
VSS VID[1] VID[2] VSS VSS VCC VSS VCC VSS VCCP VSS VCCP VSS VCCP VSS VCCP VSS VCC VSS VCC VSS VCC TEST2 VSS D[21]# VCCA[0]
RSVD VSS VID[3] VID[4] VCC VSS VCC VSS VSS D[22]# D[17]# VSS
RS[0]# DRDY# VSS VID[5] VSS VCC VSS VCC D[16]# D[20]# VSS D[29]#
VSS LOCK# BPRI# VSS VCC VSS VCC VSS D[23]# VSS D[25]# DINV
[1]#
RS[1]# VSS HIT# HITM# VSS VCCP VSS VCC VSS DSTBN
[1]# D[31]# VSS
BNR# RS[2]# VSS DEFER# VCCP VSS VCCP VSS D[18]# DSTBP
[1]# VSS D[26]#
DBSY# TRDY# VSS VSS VCCP VSS VCCP D[24]# VSS D[28]# D[19]#
VCCA[2] ADS# VSS BR0# VCCP VSS VCCP VSS VSS D[27]# D[30]# VSS
REQ
[3]# VSS REQ
[1]# A[3]# VSS VCCP VSS VCCP VCCQ[0] VSS COMP
[0] COMP
[1]
VSS REQ
[0]# A[6]# VSS VCCP VSS VCCP VSS D[39]# D[37]# VSS D[38]#
REQ
[4]# REQ
[2]# VSS A[9]# VSS VCCP VSS VCCP VSS DINV
[2]# D[34]# VSS
A[13]# VSS ADSTB
[0]# A[4]# VCC VSS VCCP VSS D[35]# VSS D[43]# D[41]#
VSS A[7]# A[5]# VSS VSS VCC VSS VCC D[36]# D[42]# VSS D[44]#
A[8]# A[10]# VSS VCCQ[1] VCC VSS VCC VSS VSS DSTBP
[2]# DSTBN
[2]# VSS
A[12]# VSS A[15]# VSS VCC VSS VCC D[45]# VSS D[47]# D[32]#
VSS A[16]# A[14]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[40]# D[33]# VSS D[46]#
COMP
[3] COMP
[2] VSS A[24]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[50]# D[48]# VSS
RSVD VSS A[20]# A[18]# VSS A[25]# A[19]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC D[51]# VSS D[52]# D[49]# VSS D[53]# VCCA[3]
VSS A[23]# A[21]# VSS A[26]# A[28]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS DINV
[3]# D[60]# VSS D[54]# D[57]# VSS GTLREF
A[30]# A[27]# VSS A[22]# ADSTB
[1]# VSS VCC
SENSE VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[59]# D[55]# VSS DSTBN
[3]# DSTBP
[3]# VSS
A[31]#
A[31]# VSS A[29]# A[17]# VSS VSS
SENSE RSVD VCC VSS VCC VSS VCC vss VCC VSS VCC VSS VCC VSS D[58]# VSS D[62]# D[56]# VSS D[61]# D[63]#
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
1234567891011121314151617181920212223242526
VSS VCC Other
VSS
A[11]#
VSS
TOP VIEW
VCCA[1]
Pin B2 is depopulated on the Micro-FCPGA package
RSVD
Datasheet 39
Package Mechanical Specifications and Pin Information
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
A[3]# P4 Source Synch Input/
Output
A[4]# U4 Source Synch Input/
Output
A[5]# V3 Source Synch Input/
Output
A[6]# R3 Source Synch Input/
Output
A[7]# V2 Source Synch Input/
Output
A[8]# W1 Source Synch Input/
Output
A[9]# T4 Source Synch Input/
Output
A[10]# W2 Source Synch Input/
Output
A[11]# Y4 Source Synch Input/
Output
A[12]# Y1 Source Synch Input/
Output
A[13]# U1 Source Synch Input/
Output
A[14]# AA3 Source Synch Input/
Output
A[15]# Y3 Source Synch Input/
Output
A[16]# AA2 Source Synch Input/
Output
A[17]# AF4 Source Synch Input/
Output
A[18]# AC4 Source Synch Input/
Output
A[19]# AC7 Source Synch Input/
Output
A[20]# AC3 Source Synch Input/
Output
A[21]# AD3 Source Synch Input/
Output
A[22]# AE4 Source Synch Input/
Output
A[23]# AD2 Source Synch Input/
Output
A[24]# AB4 Source Synch Input/
Output
A[25]# AC6 Source Synch Input/
Output
A[26]# AD5 Source Synch Input/
Output
A[27]# AE2 Source Synch Input/
Output
A[28]# AD6 Source Synch Input/
Output
A[29]# AF3 Source Synch Input/
Output
A[30]# AE1 Source Synch Input/
Output
A[31]# AF1 Source Synch Input/
Output
A20M# C2 CMOS Input
ADS# N2 Common
Clock Input/
Output
ADSTB[0]# U3 Source Synch Input/
Output
ADSTB[1]# AE5 Source Synch Input/
Output
BCLK[0] B15 Bus Clock Input
BCLK[1] B14 Bus Clock Input
BNR# L1 Common
Clock Input/
Output
BPM[0]# C8 Common
Clock Output
BPM[1]# B8 Common
Clock Output
BPM[2]# A9 Common
Clock Output
BPM[3]# C9 Common
Clock Input/
Output
BPRI# J3 Common
Clock Input
BR0# N4 Common
Clock Input/
Output
BSEL[1] C14 CMOS Output
BSEL[0] C16 CMOS Output
COMP[0] P25 Power/Other Input/
Output
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
Package Mechanical Specifications and Pin Information
40 Datasheet
COMP[1] P26 Power/Other Input/
Output
COMP[2] AB2 Power/Other Input/
Output
COMP[3] AB1 Power/Other Input/
Output
D[0]# A19 Source Synch Input/
Output
D[1]# A25 Source Synch Input/
Output
D[2]# A22 Source Synch Input/
Output
D[3]# B21 Source Synch Input/
Output
D[4]# A24 Source Synch Input/
Output
D[5]# B26 Source Synch Input/
Output
D[6]# A21 Source Synch Input/
Output
D[7]# B20 Source Synch Input/
Output
D[8]# C20 Source Synch Input/
Output
D[9]# B24 Source Synch Input/
Output
D[10]# D24 Source Synch Input/
Output
D[11]# E24 Source Synch Input/
Output
D[12]# C26 Source Synch Input/
Output
D[13]# B23 Source Synch Input/
Output
D[14]# E23 Source Synch Input/
Output
D[15]# C25 Source Synch Input/
Output
D[16]# H23 Source Synch Input/
Output
D[17]# G25 Source Synch Input/
Output
D[18]# L23 Source Synch Input/
Output
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
D[19]# M26 Source Synch Input/
Output
D[20]# H24 Source Synch Input/
Output
D[21]# F25 Source Synch Input/
Output
D[22]# G24 Source Synch Input/
Output
D[23]# J23 Source Synch Input/
Output
D[24]# M23 Source Synch Input/
Output
D[25]# J25 Source Synch Input/
Output
D[26]# L26 Source Synch Input/
Output
D[27]# N24 Source Synch Input/
Output
D[28]# M25 Source Synch Input/
Output
D[29]# H26 Source Synch Input/
Output
D[30]# N25 Source Synch Input/
Output
D[31]# K25 Source Synch Input/
Output
D[32]# Y26 Source Synch Input/
Output
D[33]# AA24 Source Synch Input/
Output
D[34]# T25 Source Synch Input/
Output
D[35]# U23 Source Synch Input/
Output
D[36]# V23 Source Synch Input/
Output
D[37]# R24 Source Synch Input/
Output
D[38]# R26 Source Synch Input/
Output
D[39]# R23 Source Synch Input/
Output
D[40]# AA23 Source Synch Input/
Output
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
Datasheet 41
Package Mechanical Specifications and Pin Information
D[41]# U26 Source Synch Input/
Output
D[42]# V24 Source Synch Input/
Output
D[43]# U25 Source Synch Input/
Output
D[44]# V26 Source Synch Input/
Output
D[45]# Y23 Source Synch Input/
Output
D[46]# AA26 Source Synch Input/
Output
D[47]# Y25 Source Synch Input/
Output
D[48]# AB25 Source Synch Input/
Output
D[49]# AC23 Source Synch Input/
Output
D[50]# AB24 Source Synch Input/
Output
D[51]# AC20 Source Synch Input/
Output
D[52]# AC22 Source Synch Input/
Output
D[53]# AC25 Source Synch Input/
Output
D[54]# AD23 Source Synch Input/
Output
D[55]# AE22 Source Synch Input/
Output
D[56]# AF23 Source Synch Input/
Output
D[57]# AD24 Source Synch Input/
Output
D[58]# AF20 Source Synch Input/
Output
D[59]# AE21 Source Synch Input/
Output
D[60]# AD21 Source Synch Input/
Output
D[61]# AF25 Source Synch Input/
Output
D[62]# AF22 Source Synch Input/
Output
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
D[63]# AF26 Source Synch Input/
Output
DBR# A7 CMOS Output
DBSY# M2 Common
Clock Input/
Output
DEFER# L4 Common
Clock Input
DINV[0]# D25 Source Synch Input/
Output
DINV[1]# J26 Source Synch Input/
Output
DINV[2]# T24 Source Synch Input/
Output
DINV[3]# AD20 Source Synch Input/
Output
DPSLP# B7 CMOS Input
DPWR# C19 Common
Clock Input
DRDY# H2 Common
Clock Input/
Output
DSTBN[0]# C23 Source Synch Input/
Output
DSTBN[1]# K24 Source Synch Input/
Output
DSTBN[2]# W 25 Source Synch Input/
Output
DSTBN[3]# AE24 Source Synch Input/
Output
DSTBP[0]# C22 Source Synch Input/
Output
DSTBP[1]# L24 So urce Synch Input/
Output
DSTBP[2]# W24 Source Synch Input/
Output
DSTBP[3]# AE25 Source Synch Input/
Output
FERR# D3 Open Drain Output
GTLREF AD26 Power/Other Input
HIT# K3 Common
Clock Input/
Output
HITM# K4 Common
Clock Input/
Output
IERR# A4 Open Drain Output
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
Package Mechanical Specifications and Pin Information
42 Datasheet
IGNNE# A3 CMOS Input
INIT# B5 CMOS Input
ITP_CLK[0] A16 CMOS input
ITP_CLK[1] A15 CMOS input
LINT0 D1 CMOS Input
LINT1 D4 CMOS Input
LOCK# J2 Common
Clock Input/
Output
PRDY# A10 Common
Clock Output
PREQ# B10 Common
Clock Input
PROCHOT# B17 Open Drain Output
PSI# E1 CMOS Output
PWRGOOD E4 CMOS Input
REQ[0]# R2 Source Synch Input/
Output
REQ[1]# P3 Source Synch Input/
Output
REQ[2]# T2 Source Synch Input/
Output
REQ[3]# P1 Source Synch Input/
Output
REQ[4]# T1 Source Synch Input/
Output
RESET# B11 Common
Clock Input
RS[0]# H1 Common
Clock Input
RS[1]# K1 Common
Clock Input
RS[2]# L2 Common
Clock Input
RSVD AF7 Reserved
RSVD B2 Reserved
RSVD C3 Reserved
RSVD E26 Reserved
RSVD G1 Reserved
RSVD AC1 Reserved
SLP# A6 CMOS Input
SMI# B4 CMOS Input
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
STPCLK# C6 CMOS Input
TCK A13 CMOS Input
TDI C12 CMOS Input
TDO A12 Open Drain Output
TEST1 C5 Test
TEST2 F23 Test
THERMDA B18 Power/Other
THERMDC A18 Power/Other
THERMTRIP# C17 Open Drain Output
TMS C11 CMOS Input
TRDY# M3 Common
Clock Input
TRST# B13 CMOS Input
VCC D6 Power/Other
VCC D8 Power/Other
VCC D18 Power/Other
VCC D20 Power/Other
VCC D22 Power/Other
VCC E5 Power/Other
VCC E7 Power/Other
VCC E9 Power/Other
VCC E17 Power/Other
VCC E19 Power/Other
VCC E21 Power/Other
VCC F6 Power/Other
VCC F8 Power/Other
VCC F18 Power/Other
VCC F20 Power/Other
VCC F22 Power/Other
VCC G5 Power/Other
VCC G21 Power/Other
VCC H6 Power/Other
VCC H22 Power/Other
VCC J5 Power/Other
VCC J21 Power/Other
VCC K22 Power/Other
VCC U5 Power/Other
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
Datasheet 43
Package Mechanical Specifications and Pin Information
VCC V6 Power/Other
VCC V22 Power/Other
VCC W5 Power/Other
VCC W21 Power/Other
VCC Y6 Power/Other
VCC Y22 Power/Other
VCC AA5 Power/Other
VCC AA7 Power/Other
VCC AA9 Power/Other
VCC AA11 Power/Other
VCC AA13 Power/Other
VCC AA15 Power/Other
VCC AA17 Power/Other
VCC AA19 Power/Other
VCC AA21 Power/Other
VCC AB6 Power/Other
VCC AB8 Power/Other
VCC AB10 Power/Other
VCC AB12 Power/Other
VCC AB14 Power/Other
VCC AB16 Power/Other
VCC AB18 Power/Other
VCC AB20 Power/Other
VCC AB22 Power/Other
VCC AC9 Power/Other
VCC AC11 Power/Other
VCC AC13 Power/Other
VCC AC15 Power/Other
VCC AC17 Power/Other
VCC AC19 Power/Other
VCC AD8 Power/Other
VCC AD10 Power/Other
VCC AD12 Power/Other
VCC AD14 Power/Other
VCC AD16 Power/Other
VCC AD18 Power/Other
VCC AE9 Power/Other
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
VCC AE11 Power/Other
VCC AE13 Power/Other
VCC AE15 Power/Other
VCC AE17 Power/Other
VCC AE19 Power/Other
VCC AF8 Power/Other
VCC AF10 Power/Other
VCC AF12 Power/Other
VCC AF14 Power/Other
VCC AF16 Power/Other
VCC AF18 Power/Other
VCCA[0] F26 Power/Other
VCCA[1] B1 Power/Other
VCCA[2] N1 Power/Other
VCCA[3] AC26 Power/Other
VCCP D10 Power/Other
VCCP D12 Power/Other
VCCP D14 Power/Other
VCCP D16 Power/Other
VCCP E11 Power/Other
VCCP E13 Power/Other
VCCP E15 Power/Other
VCCP F10 Power/Other
VCCP F12 Power/Other
VCCP F14 Power/Other
VCCP F16 Power/Other
VCCP K6 Power/Other
VCCP L5 Power/Other
VCCP L21 Power/Other
VCCP M6 Power/Other
VCCP M22 Power/Other
VCCP N5 Power/Other
VCCP N21 Power/Other
VCCP P6 Power/Other
VCCP P22 Power/Other
VCCP R5 Power/Other
VCCP R21 Power/Other
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
Package Mechanical Specifications and Pin Information
44 Datasheet
VCCP T6 Power/Other
VCCP T22 Power/Other
VCCP U21 Power/Other
VCCQ[0] P23 Power/Other
VCCQ[1] W4 Power/Other
VCCSENSE AE7 Power/Other Output
VID[0] E2 CMOS Output
VID[1] F2 CMOS Output
VID[2] F3 CMOS Output
VID[3] G3 CMOS Output
VID[4] G4 CMOS Output
VID[5] H4 CMOS Output
VSS A2 Power/Other
VSS A5 Power/Other
VSS A8 Power/Other
VSS A11 Power/Other
VSS A14 Power/Other
VSS A17 Power/Other
VSS A20 Power/Other
VSS A23 Power/Other
VSS A26 Power/Other
VSS B3 Power/Other
VSS B6 Power/Other
VSS B9 Power/Other
VSS B12 Power/Other
VSS B16 Power/Other
VSS B19 Power/Other
VSS B22 Power/Other
VSS B25 Power/Other
VSS C1 Power/Other
VSS C4 Power/Other
VSS C7 Power/Other
VSS C10 Power/Other
VSS C13 Power/Other
VSS C15 Power/Other
VSS C18 Power/Other
VSS C21 Power/Other
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
VSS C24 Power/Other
VSS D2 Power/Other
VSS D5 Power/Other
VSS D7 Power/Other
VSS D9 Power/Other
VSS D11 Power/Other
VSS D13 Power/Other
VSS D15 Power/Other
VSS D17 Power/Other
VSS D19 Power/Other
VSS D21 Power/Other
VSS D23 Power/Other
VSS D26 Power/Other
VSS E3 Power/Other
VSS E6 Power/Other
VSS E8 Power/Other
VSS E10 Power/Other
VSS E12 Power/Other
VSS E14 Power/Other
VSS E16 Power/Other
VSS E18 Power/Other
VSS E20 Power/Other
VSS E22 Power/Other
VSS E25 Power/Other
VSS F1 Power/Other
VSS F4 Power/Other
VSS F5 Power/Other
VSS F7 Power/Other
VSS F9 Power/Other
VSS F11 Power/Other
VSS F13 Power/Other
VSS F15 Power/Other
VSS F17 Power/Other
VSS F19 Power/Other
VSS F21 Power/Other
VSS F24 Power/Other
VSS G2 Power/Other
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
Datasheet 45
Package Mechanical Specifications and Pin Information
VSS G6 Power/Other
VSS G22 Power/Other
VSS G23 Power/Other
VSS G26 Power/Other
VSS H3 Power/Other
VSS H5 Power/Other
VSS H21 Power/Other
VSS H25 Power/Other
VSS J1 Power/Other
VSS J4 Power/Other
VSS J6 Power/Other
VSS J22 Power/Other
VSS J24 Power/Other
VSS K2 Power/Other
VSS K5 Power/Other
VSS K21 Power/Other
VSS K23 Power/Other
VSS K26 Power/Other
VSS L3 Power/Other
VSS L6 Power/Other
VSS L22 Power/Other
VSS L25 Power/Other
VSS M1 Power/Other
VSS M4 Power/Other
VSS M5 Power/Other
VSS M21 Power/Other
VSS M24 Power/Other
VSS N3 Power/Other
VSS N6 Power/Other
VSS N22 Power/Other
VSS N23 Power/Other
VSS N26 Power/Other
VSS P2 Power/Other
VSS P5 Power/Other
VSS P21 Power/Other
VSS P24 Power/Other
VSS R1 Power/Other
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
VSS R4 Power/Other
VSS R6 Power/Other
VSS R22 Power/Other
VSS R25 Power/Other
VSS T3 Power/Other
VSS T5 Power/Other
VSS T21 Power/Other
VSS T23 Power/Other
VSS T26 Power/Other
VSS U2 Power/Other
VSS U6 Power/Other
VSS U22 Power/Other
VSS U24 Power/Other
VSS V1 Power/Other
VSS V4 Power/Other
VSS V5 Power/Other
VSS V21 Power/Other
VSS V25 Power/Other
VSS W3 Power/Other
VSS W6 Power/Other
VSS W22 Power/Other
VSS W23 Power/Other
VSS W26 Power/Other
VSS Y2 Power/Other
VSS Y5 Power/Other
VSS Y21 Power/Other
VSS Y24 Power/Other
VSS AA1 Power/Other
VSS AA4 Power/Other
VSS AA6 Power/Other
VSS AA8 Power/Other
VSS AA10 Power/Other
VSS AA12 Power/Other
VSS AA14 Power/Other
VSS AA16 Power/Other
VSS AA18 Power/Other
VSS AA20 Power/Other
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
Package Mechanical Specifications and Pin Information
46 Datasheet
VSS AA22 Power/Other
VSS AA25 Power/Other
VSS AB3 Power/Other
VSS AB5 Power/Other
VSS AB7 Power/Other
VSS AB9 Power/Other
VSS AB11 Power/Other
VSS AB13 Power/Other
VSS AB15 Power/Other
VSS AB17 Power/Other
VSS AB19 Power/Other
VSS AB21 Power/Other
VSS AB23 Power/Other
VSS AB26 Power/Other
VSS AC2 Power/Other
VSS AC5 Power/Other
VSS AC8 Power/Other
VSS AC10 Power/Other
VSS AC12 Power/Other
VSS AC14 Power/Other
VSS AC16 Power/Other
VSS AC18 Power/Other
VSS AC21 Power/Other
VSS AC24 Power/Other
VSS AD1 Power/Other
VSS AD4 Power/Other
VSS AD7 Power/Other
VSS AD9 Power/Other
VSS AD11 Power/Other
VSS AD13 Power/Other
VSS AD15 Power/Other
VSS AD17 Power/Other
VSS AD19 Power/Other
VSS AD22 Power/Other
VSS AD25 Power/Other
VSS AE3 Power/Other
VSS AE6 Power/Other
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
VSS AE8 Power/Other
VSS AE10 Power/Other
VSS AE12 Power/Other
VSS AE14 Power/Other
VSS AE16 Power/Other
VSS AE18 Power/Other
VSS AE20 Power/Other
VSS AE23 Power/Other
VSS AE26 Power/Other
VSS AF2 Power/Other
VSS AF5 Power/Other
VSS AF9 Power/Other
VSS AF11 Power/Other
VSS AF13 Power/Other
VSS AF15 Power/Other
VSS AF17 Power/Other
VSS AF19 Power/Other
VSS AF21 Power/Other
VSS AF24 Power/Other
VSSSENSE AF6 Power/Other Output
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
A2 VSS Power/Other
A3 IGNNE# CMOS Input
A4 IERR# Open Drain Output
A5 VSS Power/Other
A6 SLP# CMOS Input
A7 DBR# CMOS Output
A8 VSS Power/Other
A9 BPM[2]# Common
Clock Output
A10 PRDY# Common
Clock Output
A11 VSS Power/Other
A12 TDO Open Drain Output
A13 TCK CMOS Input
Table 14. Pin Listing by Pin Name
Pin Name Pin # Signal
Buffer Type Direction
Datasheet 47
Package Mechanical Specifications and Pin Information
A14 VSS Power/Other
A15 ITP_CLK[1] CMOS input
A16 ITP_CLK[0] CMOS input
A17 VSS Power/Other
A18 THERMDC Power/Other
A19 D[0]# Source Synch Input/
Output
A20 VSS Power/Other
A21 D[6]# Source Synch Input/
Output
A22 D[2]# Source Synch Input/
Output
A23 VSS Power/Other
A24 D[4]# Source Synch Input/
Output
A25 D[1]# Source Synch Input/
Output
A26 VSS Power/Other
AA1 VSS Power/Other
AA2 A[16]# Source Synch Input/
Output
AA3 A[14]# Source Synch Input/
Output
AA4 VSS Power/Other
AA5 VCC Power/Other
AA6 VSS Power/Other
AA7 VCC Power/Other
AA8 VSS Power/Other
AA9 VCC Power/Other
AA10 VSS Power/Other
AA11 VCC Power/Other
AA12 VSS Power/Other
AA13 VCC Power/Other
AA14 VSS Power/Other
AA15 VCC Power/Other
AA16 VSS Power/Other
AA17 VCC Power/Other
AA18 VSS Power/Other
AA19 VCC Power/Other
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
AA20 VSS Power/Other
AA21 VCC Power/Other
AA22 VSS Power/Other
AA23 D[40]# Source Synch Input/
Output
AA24 D[33]# Source Synch Input/
Output
AA25 VSS Power/Other
AA26 D[46]# Source Synch Input/
Output
AB1 COMP[3] Power/Other Input/
Output
AB2 COMP[2] Power/Other Input/
Output
AB3 VSS Power/Other
AB4 A[24]# Source Synch Input/
Output
AB5 VSS Power/Other
AB6 VCC Power/Other
AB7 VSS Power/Other
AB8 VCC Power/Other
AB9 VSS Power/Other
AB10 VCC Power/Other
AB11 VSS Power/Other
AB12 VCC Power/Other
AB13 VSS Power/Other
AB14 VCC Power/Other
AB15 VSS Power/Other
AB16 VCC Power/Other
AB17 VSS Power/Other
AB18 VCC Power/Other
AB19 VSS Power/Other
AB20 VCC Power/Other
AB21 VSS Power/Other
AB22 VCC Power/Other
AB23 VSS Power/Other
AB24 D[50]# Source Synch Input/
Output
AB25 D[48]# Source Synch Input/
Output
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
Package Mechanical Specifications and Pin Information
48 Datasheet
AB26 VSS Power/Other
AC1 RSVD Reserved
AC2 VSS Power/Other
AC3 A[20]# Source Synch Input/
Output
AC4 A[18]# Source Synch Input/
Output
AC5 VSS Power/Other
AC6 A[25]# Source Synch Input/
Output
AC7 A[19]# Source Synch Input/
Output
AC8 VSS Power/Other
AC9 VCC Power/Other
AC10 VSS Power/Other
AC11 VCC Power/Other
AC12 VSS Power/Other
AC13 VCC Power/Other
AC14 VSS Power/Other
AC15 VCC Power/Other
AC16 VSS Power/Other
AC17 VCC Power/Other
AC18 VSS Power/Other
AC19 VCC Power/Other
AC20 D[51]# Source Synch Input/
Output
AC21 VSS Power/Other
AC22 D[52]# Source Synch Input/
Output
AC23 D[49]# Source Synch Input/
Output
AC24 VSS Power/Other
AC25 D[53]# Source Synch Input/
Output
AC26 VCCA[3] Power/Other
AD1 VSS Power/Other
AD2 A[23]# Source Synch Input/
Output
AD3 A[21]# Source Synch Input/
Output
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
AD4 VSS Power/Other
AD5 A[26]# Source Synch Input/
Output
AD6 A[28]# Source Synch Input/
Output
AD7 VSS Power/Other
AD8 VCC Power/Other
AD9 VSS Power/Other
AD10 VCC Power/Other
AD11 VSS Power/Other
AD12 VCC Power/Other
AD13 VSS Power/Other
AD14 VCC Power/Other
AD15 VSS Power/Other
AD16 VCC Power/Other
AD17 VSS Power/Other
AD18 VCC Power/Other
AD19 VSS Power/Other
AD20 DINV[3]# Source Synch Input/
Output
AD21 D[60]# Source Sy nc h Input/
Output
AD22 VSS Power/Other
AD23 D[54]# Source Sy nc h Input/
Output
AD24 D[57]# Source Sy nc h Input/
Output
AD25 VSS Power/Other
AD26 GTLREF Power/Other
AE1 A[30]# Source Synch Input/
Output
AE2 A[27]# Source Synch Input/
Output
AE3 VSS Power/Other
AE4 A[22]# Source Synch Input/
Output
AE5 ADSTB[1]# Source Synch Input/
Output
AE6 VSS Power/Other
AE7 VCCSENSE Power/Other Output
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
Datasheet 49
Package Mechanical Specifications and Pin Information
AE8 VSS Power/Other
AE9 VCC Power/Other
AE10 VSS Power/Other
AE11 VCC Power/Other
AE12 VSS Power/Other
AE13 VCC Power/Other
AE14 VSS Power/Other
AE15 VCC Power/Other
AE16 VSS Power/Other
AE17 VCC Power/Other
AE18 VSS Power/Other
AE19 VCC Power/Other
AE20 VSS Power/Other
AE21 D[59]# Source Synch Input/
Output
AE22 D[55]# Source Synch Input/
Output
AE23 VSS Power/Other
AE24 DSTBN[3]# Source Synch Input/
Output
AE25 DSTBP[3]# Source Synch Input/
Output
AE26 VSS Power/Other
AF1 A[31]# Source Synch Input/
Output
AF2 VSS Power/Other
AF3 A[29]# Source Synch Input/
Output
AF4 A[17]# Source Synch Input/
Output
AF5 VSS Power/Other
AF6 VSSSENSE Power/Other Output
AF7 RSVD Reserved
AF8 VCC Power/Other
AF9 VSS Power/Other
AF10 VCC Power/Other
AF11 VSS Power/Other
AF12 VCC Power/Other
AF13 VSS Power/Other
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
AF14 VCC Power/Other
AF15 VSS Power/Other
AF16 VCC Power/Other
AF17 VSS Power/Other
AF18 VCC Power/Other
AF19 VSS Power/Other
AF20 D[58]# Source Synch Input/
Output
AF21 VSS Power/Other
AF22 D[62]# Source Synch Input/
Output
AF23 D[56]# Source Synch Input/
Output
AF24 VSS Power/Other
AF25 D[61]# Source Synch Input/
Output
AF26 D[63]# Source Synch Input/
Output
B1 VCCA[1] Power/Other
B2 RSVD Reserved
B3 VSS Power/Other
B4 SMI# CMOS Input
B5 INIT# CMOS Input
B6 VSS Power/Other
B7 DPSLP# CMOS Input
B8 BPM[1]# Common
Clock Output
B9 VSS Power/Other
B10 PREQ# Common
Clock Input
B11 RESET# Common
Clock Input
B12 VSS Power/Other
B13 TRST# CMOS Input
B14 BCLK[1] Bus Clock Input
B15 BCLK[0] Bus Clock Input
B16 VSS Power/Other
B17 PROCHOT# Open Drain Output
B18 THERMDA Power/Other
B19 VSS Power/Other
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
Package Mechanical Specifications and Pin Information
50 Datasheet
B20 D[7]# Source Synch Input/
Output
B21 D[3]# Source Synch Input/
Output
B22 VSS Power/Other
B23 D[13]# Source Synch Input/
Output
B24 D[9]# Source Synch Input/
Output
B25 VSS Power/Other
B26 D[5]# Source Synch Input/
Output
C1 VSS Power/Other
C2 A20M# CMOS Input
C3 RSVD Reserved
C4 VSS Power/Other
C5 TEST1 Test
C6 STPCLK# CMOS Input
C7 VSS Power/Other
C8 BPM[0]# Common
Clock Output
C9 BPM[3]# Common
Clock Input/
Output
C10 VSS Power/Other
C11 TMS CMOS Input
C12 TDI CMOS Input
C13 VSS Power/Other
C14 BSEL[1] CMOS Output
C15 VSS Power/Other
C16 BSEL[0] CMOS Output
C17 THERMTRIP# Open Drain Output
C18 VSS Power/Other
C19 DPWR# Common
Clock Input
C20 D[8]# Source Synch Input/
Output
C21 VSS Power/Other
C22 DSTBP[0]# Source Synch Input/
Output
C23 DSTBN[0]# Source Synch Input/
Output
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
C24 VSS Power/Other
C25 D[15]# Source Sy nc h Input/
Output
C26 D[12]# Source Sy nc h Input/
Output
D1 LINT0 CMOS Input
D2 VSS Power/Other
D3 FERR# Open Drain Output
D4 LINT1 CMOS Input
D5 VSS Power/Other
D6 VCC Power/Other
D7 VSS Power/Other
D8 VCC Power/Other
D9 VSS Power/Other
D10 VCCP Power/Other
D11 VSS Power/Other
D12 VCCP Power/Other
D13 VSS Power/Other
D14 VCCP Power/Other
D15 VSS Power/Other
D16 VCCP Power/Other
D17 VSS Power/Other
D18 VCC Power/Other
D19 VSS Power/Other
D20 VCC Power/Other
D21 VSS Power/Other
D22 VCC Power/Other
D23 VSS Power/Other
D24 D[10]# Source Synch Input/
Output
D25 DINV[0]# Source Synch Input/
Output
D26 VSS Power/Other
E1 PSI# CMOS Output
E2 VID[0] CMOS Output
E3 VSS Power/Other
E4 PWRGOOD CMOS Input
E5 VCC Power/Other
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
Datasheet 51
Package Mechanical Specifications and Pin Information
E6 VSS Power/Other
E7 VCC Power/Other
E8 VSS Power/Other
E9 VCC Power/Other
E10 VSS Power/Other
E11 VCCP Power/Other
E12 VSS Power/Other
E13 VCCP Power/Other
E14 VSS Power/Other
E15 VCCP Power/Other
E16 VSS Power/Other
E17 VCC Power/Other
E18 VSS Power/Other
E19 VCC Power/Other
E20 VSS Power/Other
E21 VCC Power/Other
E22 VSS Power/Other
E23 D[14]# Source Synch Input/
Output
E24 D[11]# Source Synch Input/
Output
E25 VSS Power/Other
E26 RSVD Reserved
F1 VSS Power/Other
F2 VID[1] CMOS Output
F3 VID[2] CMOS Output
F4 VSS Power/Other
F5 VSS Power/Other
F6 VCC Power/Other
F7 VSS Power/Other
F8 VCC Power/Other
F9 VSS Power/Other
F10 VCCP Power/Other
F11 VSS Power/Other
F12 VCCP Power/Other
F13 VSS Power/Other
F14 VCCP Power/Other
F15 VSS Power/Other
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
F16 VCCP Power/Other
F17 VSS Power/Other
F18 VCC Power/Other
F19 VSS Power/Other
F20 VCC Power/Other
F21 VSS Power/Other
F22 VCC Power/Other
F23 TEST2 Test
F24 VSS Power/Other
F25 D[21]# Source Synch Input/
Output
F26 VCCA[0] Power/Other
G1 RSVD Reserved
G2 VSS Power/Other
G3 VID[3] CMOS Output
G4 VID[4] CMOS Output
G5 VCC Power/Other
G6 VSS Power/Other
G21 VCC Power/Other
G22 VSS Power/Other
G23 VSS Power/Other
G24 D[22]# Source Synch Input/
Output
G25 D[17]# Source Synch Input/
Output
G26 VSS Power/Other
H1 RS[0]# Common
Clock Input
H2 DRDY# Common
Clock Input/
Output
H3 VSS Power/Other
H4 VID[5] CMOS Output
H5 VSS Power/Other
H6 VCC Power/Other
H21 VSS Power/Other
H22 VCC Power/Other
H23 D[16]# Source Synch Input/
Output
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
Package Mechanical Specifications and Pin Information
52 Datasheet
H24 D[20]# Source Synch Input/
Output
H25 VSS Power/Other
H26 D[29]# Source Synch Input/
Output
J1 VSS Power/Other
J2 LOCK# Common
Clock Input/
Output
J3 BPRI# Common
Clock Input
J4 VSS Power/Other
J5 VCC Power/Other
J6 VSS Power/Other
J21 VCC Power/Other
J22 VSS Power/Other
J23 D[23]# Source Synch Input/
Output
J24 VSS Power/Other
J25 D[25]# Source Synch Input/
Output
J26 DINV[1]# Source Synch Input/
Output
K1 RS[1]# Common
Clock Input
K2 VSS Power/Other
K3 HIT# Common
Clock Input/
Output
K4 HITM# Common
Clock Input/
Output
K5 VSS Power/Other
K6 VCCP Power/Other
K21 VSS Power/Other
K22 VCC Power/Other
K23 VSS Power/Other
K24 DSTBN[1]# Source Synch Input/
Output
K25 D[31]# Source Synch Input/
Output
K26 VSS Power/Other
L1 BNR# Common
Clock Input/
Output
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
L2 RS[2]# Common
Clock Input
L3 VSS Power/Other
L4 DEFER# Common
Clock Input
L5 VCCP Power/Other
L6 VSS Power/Other
L21 VCCP Power/Other
L22 VSS Power/Other
L23 D[18]# Source Synch Input/
Output
L24 DSTBP[ 1 ]# Source Synch Input/
Output
L25 VSS Power/Other
L26 D[26]# Source Synch Input/
Output
M1 VSS Power/Other
M2 DBSY# Common
Clock Input/
Output
M3 TRDY# Common
Clock Input
M4 VSS Power/Other
M5 VSS Power/Other
M6 VCCP Power/Other
M21 VSS Power/Other
M22 VCCP Power/Other
M23 D[24]# Source Synch Input/
Output
M24 VSS Power/Other
M25 D[28]# Source Synch Input/
Output
M26 D[19]# Source Synch Input/
Output
N1 VCCA[2] Power/Other
N2 ADS# Common
Clock Input/
Output
N3 VSS Power/Other
N4 BR0# Common
Clock Input/
Output
N5 VCCP Power/Other
N6 VSS Power/Other
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
Datasheet 53
Package Mechanical Specifications and Pin Information
N21 VCCP Power/Other
N22 VSS Power/Other
N23 VSS Power/Other
N24 D[27]# Source Synch Input/
Output
N25 D[30]# Source Synch Input/
Output
N26 VSS Power/Other
P1 REQ[3]# Source Synch Input/
Output
P2 VSS Power/Other
P3 REQ[1]# Source Synch Input/
Output
P4 A[3]# Source Synch Input/
Output
P5 VSS Power/Other
P6 VCCP Power/Other
P21 VSS Power/Other
P22 VCCP Power/Other
P23 VCCQ[0] Power/Other
P24 VSS Power/Other
P25 COMP[0] Power/Other Input/
Output
P26 COMP[1] Power/Other Input/
Output
R1 VSS Power/Other
R2 REQ[0]# Source Synch Input/
Output
R3 A[6]# Source Synch Input/
Output
R4 VSS Power/Other
R5 VCCP Power/Other
R6 VSS Power/Other
R21 VCCP Power/Other
R22 VSS Power/Other
R23 D[39]# Source Synch Input/
Output
R24 D[37]# Source Synch Input/
Output
R25 VSS Power/Other
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
R26 D[38]# Source Synch Input/
Output
T1 REQ[4]# Source Synch Input/
Output
T2 REQ[2]# Source Synch Input/
Output
T3 VSS Power/Other
T4 A[9]# Source Synch Input/
Output
T5 VSS Power/Other
T6 VCCP Power/Other
T21 VSS Power/Other
T22 VCCP Power/Other
T23 VSS Power/Other
T24 DINV[2]# CMOS Input/
Output
T25 D[34]# Source Synch Input/
Output
T26 VSS Power/Other
U1 A[13]# Source Synch Input/
Output
U2 VSS Power/Other
U3 ADSTB[0]# Source Synch Input/
Output
U4 A[4]# Source Synch Input/
Output
U5 VCC Power/Other
U6 VSS Power/Other
U21 VCCP Power/Other
U22 VSS Power/Other
U23 D[35]# Source Synch Input/
Output
U24 VSS Power/Other
U25 D[43]# Source Synch Input/
Output
U26 D[41]# Source Synch Input/
Output
V1 VSS Power/Other
V2 A[7]# Source Synch Input/
Output
V3 A[5]# Source Synch Input/
Output
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
Package Mechanical Specifications and Pin Information
54 Datasheet
V4 VSS Power/Other
V5 VSS Power/Other
V6 VCC Power/Other
V21 VSS Power/Other
V22 VCC Power/Other
V23 D[36]# Source Synch Input/
Output
V24 D[42]# Source Synch Input/
Output
V25 VSS Power/Other
V26 D[44]# Source Synch Input/
Output
W1 A[8]# Source Synch Input/
Output
W2 A[10]# Source Synch Input/
Output
W3 VSS Power/Other
W4 VCCQ[1] Power/Other
W5 VCC Power/Other
W6 VSS Power/Other
W21 VCC Power/Other
W22 VSS Power/Other
W23 VSS Power/Other
W24 DSTBP[2]# Source Synch Input/
Output
W25 DSTBN[2]# Source Synch Input/
Output
W26 VSS Power/Other
Y1 A[12]# Source Synch Input/
Output
Y2 VSS Power/Other
Y3 A[15]# Source Synch Input/
Output
Y4 A[11]# Source Synch Input/
Output
Y5 VSS Power/Other
Y6 VCC Power/Other
Y21 VSS Power/Other
Y22 VCC Power/Other
Y23 D[45]# Source Synch Input/
Output
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
Y24 VSS Power/Other
Y25 D[47]# Source Sync h Input/
Output
Y26 D[32]# Source Sync h Input/
Output
Table 15. Pin Listing by Pin Number
Pin # Pin Name Signal Buffer
Type Direction
Datasheet 55
Package Mechanical Specifications and Pin Information
4.2 Alphabetical Signals Reference
Table 16. Signal Description (Sheet 1 of 8)
Name Type Description
A[31:3]# Input/
Output
A[31:3]# (Address) define a 232-byte physical memory address
space. In sub-phase 1 of the address phase, these pins transmit the
address of a transaction. In sub-phase 2, these pins transmit
transaction type information. These signals must connect the
appropriate pins of both agents on the Intel® Celeron® M processor
FSB. A[31:3]# are source synchronous signals and are latched into
the receiving buffers by ADSTB[1:0]#. Address signals are used as
straps which are sampled before RESET# is deasserted.
A20M# Input
If A20M# (Address- 20 Mask) is assert ed, the processor masks
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address wrap-
around at the 1-Mbyte bounda ry. Assertion of A20M# is only
supported in real mode.
A20M# is an asynch ronous sign al. Howev er, to ensure recognition of
this signal following an Input/Output write instruct ion, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
ADS# Input/
Output
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[31:3]# and REQ[4:0]# pins. All bus
agents observe the ADS# activation to begin parity ch ecking,
protocol checking, address decode, internal snoop, or deferred reply
ID match operations associated with the new transaction.
ADSTB[1:0]# Input/
Output
Address strobes are used to latch A[31:3]# and REQ[4:0]# on their
rising and falling edges. Strobes are associated with signals as
shown below.
BCLK[1:0] Input
The differential pair BCLK (Bus Clock) determines the FSB frequency .
All FSB agents must receive these signals to drive their outputs and
latch their inputs.
All external timing parameters are specified with respect to the rising
edge of BCLK0 crossing VCROSS.
BNR# Input/
Output
BNR# (Block Next Request) is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus
stall, the current bus owner cannot issue any new transactions.
BPM[2:0]#
BPM[3]
Output
Input/
Output
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor which indicate
the status of breakpoints and programmable counters used for
monitoring processor performance. BPM[3:0]# should connect the
appropriate pins of all Celeron M FSB agents.This includes debug or
performance monitoring tools.
Signals Associated
Strobe
REQ[4:0]#, A[16:3]# ADSTB[0]#
A[31:17]# ADSTB[1]#
Package Mechanical Specifications and Pin Information
56 Datasheet
BPRI# Input
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
FSB. It must connect the appropriate pins of both FSB agents.
Observing BPRI# active (as asserted by the priority agent) causes
the other agent to stop issuing new requests, unless such requests
are part of an ongoing locked operation. The priority agent keeps
BPRI# asserted until all of its requests are complete d, th e n rel eas es
the bus by deasserting BPRI#.
BR0# Input/
Output
BR0# is used by the processor to request the bus. The arbitration is
done between Celeron M (Symmetric Agent) and Intel® 915/910
Express Chipset and Intel® 852/855 Chipset families (High Priority
Agent).
BSEL[1:0] Output
The BSEL[1:0] signals are used to select the frequency of the
processor input clock(BCLK[1:0]. Th ese signal s should be conn ect ed
to the clock chip and Intel 915GM/GMS/PM & 910GML Express
Chipsets on the platform.
These signals must be left unconnected on Intel 852/855 Chipset
family-based platforms.
COMP[3:0] Analog COMP[3:0] must be terminated on the system board using precision
(1% tolerance) resistors.
D[63:0]# Input/
Output
D[63:0]# (Data) ar e the data signal s. These signals provide a 64-bit
data path between the FSB agents, and must connect th e
appropriate pins on both agents. The data driver asserts DRDY# to
indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four
times in a co mmon cloc k period. D[ 63:0]# are latched off the falling
edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data
signals correspond to a pair of one DSTBP# and one DSTBN#. The
following table shows the grouping of data signals to data strobes
and DINV#.
Furthermore, the DINV# pins determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DINV#
signal. When the DINV# signal is active, the corresponding data
group is inverted and therefore sampled active high.
DBR# Output
DBR# (Data Bus Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by a
debug port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is a no
connect in the system. DBR# is not a processor signal.
Table 16. Signal Description (Sheet 2 of 8)
Name Type Description
Quad-Pumped Signal Groups
Data
Group DSTBN#/
DSTBP# DINV#
D[15:0]# 0 0
D[31:16]# 1 1
D[47:32]# 2 2
D[63:48]# 3 3
Datasheet 57
Package Mechanical Specifications and Pin Information
DBSY# Input/
Output
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the FSB to indicate that the data bus is in use. The
data bus is released after DBSY# is deasserted. This signal must
connect the appropriate pins on both FSB agents.
DEFER# Input
DEFER# is asserted by an agent to indicate that a transaction cannot
be guaranteed in-order completion. Assertion of DEFER# is normally
the responsibility of the addres sed memory or Input/Output agent.
This signal mu st connect the appropriate pins of both FSB agents.
DINV[3:0]# Input/
Output
DINV[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals. The DINV[3:0]#
signals are activated when the data on the data bus is inverted. The
bus agent will invert the data bus signals if more than half the bits,
within the covered group, would change level in the next cycle.
DPSLP# Input
DPSLP# when asserted on the platform causes the processor to
transition from the Sleep State to the Deep Sleep state. In order to
return to the Sleep state, DPSLP# must be deasserted. DPSLP# is
driven by the ICH-M component and also connects to the MCH-M
component.
DPWR# Input DPWR# is a control signal from the Intel chipset used to reduce
power on the Celeron M data bus input buffers.
DRDY# Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be deasserted to insert idle clocks.
This signal mu st connect the appropriate pins of both FSB agents.
DSTBN[3:0]
#Input/
Output
Data strobe used to latch in D[63:0]#.
Table 16. Signal Description (Sheet 3 of 8)
Name Type Description
DINV[3:0]# Assignment to Data Bus
Bus Signal Data Bus
Signals
DINV[3]# D[63:48]#
DINV[2]# D[47:32]#
DINV[1]# D[31:16]#
DINV[0]# D[15:0]#
Signals Associated
Strobe
D[15:0]#, DINV[0]# DSTBN[0]#
D[31:16]#, DINV[1]# DSTBN[1]#
D[47:32]#, DINV[2]# DSTBN[2]#
D[63:48]#, DINV[3]# DSTBN[3]#
Package Mechanical Specifications and Pin Information
58 Datasheet
DSTBP[3:0]# Input/
Output
Data strobe use d to latch in D[63:0]#.
FERR#/PBE# Output
FERR# (Floating-point Error)PBE#(Pending Break Event) is a
multiplexed signal and its meaning is qualified with STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating point
when the processor detects an unmasked floating-point error. FERR#
is similar to the ERROR# signal on the Intel 387 coproces sor, and is
included for compatibility with systems using MS-DOS*-type
floating-point error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a pending
break event waiting for service. The assertion of FERR#/PBE#
indicates that the processor should be returned to the Normal state.
When FERR#/PBE# is asserted, indicating a break event, it will
remain asserted until STPCLK# is deasserted. Assertion of PREQ#
when STPCLK# is active will also cause an FERR# break event.
For additional information on the pending break event functionality,
including identification of support of the feature and enable/disable
information, refer to Volume 3 of the Intel® Architecture Software
developer’s manual and the Intel® Processor Identification and
CPUID Instruction application note.
GTLREF Input GTLREF determines the signal reference level for AGTL+ input pins.
GTLREF should be set at 2/3 VCCP
. GTLREF is used by the AGTL+
receivers to determine if a signal is a logical 0 or logical 1.
HIT#
HITM#
Input/
Output
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
snoop operation results. Either FSB agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can
be continued by reasserting HIT# and HITM# together.
IERR# Output
IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the FSB. This transaction may optionally
be converted to an external error signal (e.g., NMI) by system core
logic. The processor will keep IERR# asserted until the assertion of
RESET#, BINIT#, or INIT#.
IGNNE# Input
IGNNE# (Ignore Numeric Error) is as serted to force the processor to
ignore a numeric error and continue to execute noncontrol floating -
point instructions. If IGNNE# is deasserted, the processor generates
an exception on a noncontrol floating-point instruction if a previous
floating-point instruction c a used an error. IGNNE# has no effect
when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
Table 16. Signal Description (Sheet 4 of 8)
Name Type Description
Signals Associated
Strobe
D[15:0]#, DINV[0]# DSTBP[0]#
D[31:16]#, DINV[1]# DSTBP[1]#
D[47:32]#, DINV[2]# DSTBP[2]#
D[63:48]#, DINV[3]# DSTBP[3]#
Datasheet 59
Package Mechanical Specifications and Pin Information
INIT# Input
INIT# (Initialization), when asserted, resets integer registers inside
the processor without affecting its internal caches or floating-point
registers. The processor then begins execution at the power-on
Reset vector configured during power-on configuration. The
processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal. However, to ensure
recognition of this signal following an Input/Output W rite instructio n,
it must be valid along with the TRDY# assertion of the corresponding
Input/Output Write bus transaction. INIT# must conn ect the
appropriate pins of both FSB agents.
If INIT# is sampled active on the active to inactive transition of
RESET#, then th e processor executes its Built-in Self-Test (BIST).
ITP_CLK[1:0] Input
ITP_CLK[1:0] are copies of BCLK that are used only in processor
systems where no debug port is implemented on the system board.
ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port
implemented on an inte rposer. If a debug port is implemented in the
system, ITP_ CLK[1:0] are no connect s in the system. These are not
processor signals.
LINT[1:0] Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins
of all APIC Bus agents. When the APIC is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1
becomes NMI, a nonmaskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the Celeron processor.
Both signals are asynchronous.
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK# Input/
Output
LOCK# indicates to the system that a transaction must occur
atomically . This signal must connect the appropriate pins of both FSB
agents. For a locked sequence of transactions, LOCK# is asserted
from the beginning of the first transaction to the end of the last
transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of
the FSB, it will w ait until it obse rves LOCK# deass erted. This enables
symmetric agents to retain ownership of the FSB throughout the bus
locked operation and ensure the atomic ity of lock.
PRDY# Output Probe Ready signal used by debug tools to determine processor
debug readiness.
PREQ# Input Probe R equest signal used by debug tools to request debug operation
of the processor.
PROCHOT# Output
PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that the processor has
reached its maximum safe operating temperature. This indicates that
the processor Thermal Control Circuit has been activated, if enabled.
See Chapter 5 for more details.
PSI# Output Processor Power Status Indicator (PSI) signal. This signal is asserted
when the processor is in a lower state (Deep Sleep). See
Section 2.1.4 for more details.
Table 16. Signal Description (Sheet 5 of 8)
Name Type Description
Package Mechanical Specifications and Pin Information
60 Datasheet
PWRGOOD Input
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and power
supplies are stable and within their specificati ons. Clean impl ies that
the signal will remain low (capable of sinking leakage cur rent),
without glitches, from the time that the power supplies are turned on
until they come within specification. The signal must then transition
monotonically to a high state.
The PWRGOOD signal must be supplied to the processor; it is used to
protect internal circuits against voltage sequencing issues. It should
be driven high throughout boundary scan operation.
REQ[4:0]# Input/
Output
REQ[4:0]# (Request Command) must connec t the appropriate pins
of both FSB agents. They are asserted by the current bus owner to
define the currently active transaction type. These signals are source
synchronous to ADSTB[0]#.
RESET# Input
Asserting the RESET# signal resets the process o r to a known state
and invalidates its internal caches without writing back any of their
contents. For a power -on Reset, RESET# must stay active for at leas t
two milliseconds after VCC and BCLK have reached their proper
specifications. On observing active RESET#, both FSB agents will
deassert their outputs within two clocks. All processor straps must be
valid within the specified setup time before RESET# is deasserted.
RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent (the
agent responsible for completion of the current transaction), and
must connect the appropriate pins of both FSB agents.
RSVD Reserved
/No
Connect
These pins are RESERVED and must be left unconnected on the
board. However, it is recommended that routing channels to these
pins on the board be kept open for possible future use.
SLP# Input
SLP# (Sleep), when asserted in Stop-Grant state, causes the
processor to enter the Sleep state. During Sleep state, the processor
stops providing internal clock signals to all units, leaving only the
Phase-Locked Loop (PLL) still operating. Processors in this state will
not recognize snoops or interrupts. The processor will recognize only
assertion of the RESET# signal, deassertion of SLP#, and removal of
the BCLK input while in Sleep state. If SLP# is deasserted, th e
processor exits Sleep state and returns to Stop-Grant state,
restarting its internal clock signals to the bus and processor core
units. If DPSLP# is asserted while in th e Sleep state, the processor
will exit the Slee p state and transition to the Deep Sleep st ate.
SMI# Input
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt, the
processor saves the current state and enter System Management
mode (SMM). An SMI Acknowledge transaction is is sued, and the
processor begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor
will tristate i ts outputs.
Table 16. Signal Description (Sheet 6 of 8)
Name Type Description
Datasheet 61
Package Mechanical Specifications and Pin Information
STPCLK# Input
STPCLK# (Stop Cl ock), when assert ed, causes the proc essor to enter
a low power Stop-Grant state. The processor i ssues a Stop-Grant
Acknowledge transaction, and stops providing internal clock signals
to all processor core units except the FSB and APIC units. The
processor continues to snoop bus transactions and service interrupts
while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its i nternal clock to all units and resumes
executi on. Th e assert ion of STPCLK# h as no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK Input TCK (Test Clock) provides the clock input for the processor test bus
(also known as the Test Access Port).
TDI Input TDI (Test Data In) transfers serial test data into the processor. TDI
provides the seri al input needed for JTAG specification support.
TDO Output TDO (Test Data Out) transfers serial test data out of the processor.
TDO provides the serial output needed for JTAG specification
support.
TEST1,
TEST2 Input TEST1 and TEST2 must have a stuffing option of separate pull down
resistors to VSS.
THERMDA Other Thermal Diode Anode.
THERMDC Other Thermal Diode Cathode.
THERMTRIP# Output
The processor protect s itself from catastrophic ov erheating b y use of
an internal thermal sensor. This sensor is set well above the normal
operating temperature to ensure that there are no false trips. The
processor will stop all execution when the junction temperature
exceeds appro xi mately 125 °C. This is si gnalled to the s yste m by the
THERMTRIP# (Thermal Trip) pin.
TMS Input TMS (T est Mode Select) is a JT AG specification support signal used by
debug tools.
TRDY# Input TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of both FSB agents.
TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP ) logic. TRST#
must be driven low during power on Reset.
VCC Input Processor core power supply.
VCCA[3:0] Input VCCA provides isolated power for the internal processor core PLL’s.
VCCP Input Processor I/O power supply.
VCCQ[1:0] Input Quiet power supply for on die COMP circuitry. These pins should be
connected to V CCP on the motherboard. However, these connections should
enable addition of decoup ling on the VCCQ lines if necessary.
Table 16. Signal Description (Sheet 7 of 8)
Name Type Description
Package Mechanical Specifications and Pin Information
62 Datasheet
§
VCCSENSE Output VCCSENSE is an isolated low impedance connection to processor core
power (VCC). It can be used to sense or measure power near the
silicon with little noise.
VID[5:0] Output
VID[5:0] (Voltage ID) pins are used to support automatic selection
of power supply voltages (VCC). Unlike some previous generations of
processors, thes e are CMOS signals that are driven by the Celeron M
processor. The voltage supply for these pins must be v alid before the
VR can supply VCC to the process or. Conversely, the VR outp ut must
be disabled until the voltage supply for the VID pins becomes valid.
The VID pins are needed to support the processor voltage
specification v ariations. See Table 1 for definitions of these pins. The
VR must supply the voltage that is requested by the pins, or disable
itself.
VSSSENSE Output VSSSENSE is an isolat ed low impedance connection to processor core
VSS. It can be used to sense or measure ground near the silicon with
little noise.
Table 16. Signal Description (Sheet 8 of 8)
Name Type Description
Datasheet 63
Thermal Specifications and Design Considerations
5 Thermal Specifications and
Design Considerations
The Celeron M processor requires a thermal solution to maintain temperatures within
operating limits as set forth in Table 17. Any attempt to oper ate that processor outside
these operating limits may result in permanent damage to the processor and
potentially other components in the system. As processor technology changes, thermal
management becomes increasingly crucial when building computer systems.
Maintaining the proper thermal environment is key to reliable, long-term system
operation. A complete thermal solution includes both component and system level
thermal management features. Component level thermal solutions include active or
passive heatsinks or heat exchangers attached to the processor exposed die. The
solution should make firm contact to the die while maintaining processor mechanical
specifications such as pressure. A typical system lev el thermal solution may consist of a
processor fan ducted to a heat exchanger that is th ermally coupled to the processor via
a heat pipe or direct die attachment. A secondary fan, or air from the processor fan,
may also be used to cool other platform components or lower the internal ambient
temperature within the system.
To allow for the optimal operation and long-term reliability of Intel processor-based
systems, the system/processor thermal solution should be designed such that the
processor must remain within the minimum and maximum junction temperature (Tj)
specifications at the corresponding thermal design power (TDP) v alue listed in Table 17.
Thermal solutions not design to provide this level of thermal capability may affect the
long-term reliability of the processor and system.
The maximum junction temperature is defined by an activation of the processor Intel®
Thermal Monitor. Refer to Section 5.1.3 for more details. Analysis indicates that real
applications are unlikely to cause the processor to consume the theoretical maximum
power dissipation for sustained time periods. Intel recommends that complete thermal
solution designs target the TDP indicated in Table 17. The Intel Thermal Monitor feature
is designed to help protect the processor in the unlikely event that an application
exceeds the TDP recommendation for a sustained period of time. For more details on
the usage of this featu re, refer to Section 5.1.3. In all cases, the Intel Thermal Monitor
feature must be enabled for the processor to remain within specification.
Thermal Specifications and Design Considerations
64 Datasheet
Table 17. Power Speci fications for the Celeron M Processor (Sheet 1 of 2)
Symbol Processor
Number Core Frequency
& Voltage Thermal Design Power Unit Notes
TDP
390 1.7 GHz & VCC2 27
WAt 100°C,
Notes 1,
4,5,6
380 1.6 GHz & VCC2 21
370 1.5 GHz & VCC2 21
360J 1.4 GHz & VCC2 21
360 1.4 GHz & 1.260 V 21
350J 1.3 GHz & VCC2 21
350 1.3 GHz & 1.260 V 21
383 1.1 GHz & VCC3 5.5
373 1.0 GHz & VCC3 5.5
353 900 MHz & 0.940 V 5.0
Symbol Processor
Number Parameter Min Typ Max Unit Notes
PAH,
PSGNT
Auto Halt, Stop Grant
Power at:
WAt 50°C,
Note 2,5,6
390 VCC2 11.6
380 VCC2 11.6
370 VCC2 11.6
360J VCC2 11.6
360 1.260 V 11.6
350J VCC2 11.6
350 1.260 V 11.6
383 VCC3 1.9
373 VCC3 1.9
353 0.940 V 1.9
PSLP
Sleep Power at:
WAt 50°C,
Note 2,5,6
390 VCC2 11.3
380 VCC2 11.3
370 VCC2 11.3
360J VCC2 11.3
360 1.260 V 11.3
350J VCC2 11.3
350 1.260 V 11.3
383 VCC3 1.8
373 VCC3 1.8
353 0.940 V 1.8
Datasheet 65
Thermal Specifications and Design Considerations
NOTES:
1. The Thermal Design Power (TDP) specification should be used to design the processor thermal solution.
The TDP is not the maximum theoretical power the processor can dissipate.
2. Not 100% tested. These power spec ifications are dete rmined by characterizat ion of the processo r currents
at higher temperatures and extrapolating the values for the te mperature indicated.
3. As measured by the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to
indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.
4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within
specifications.
5. Intel processor numbers are not a measure of performance. Processor numbers differentiate features
within each processor family, not across different processor families. See www.intel.com/products/
processor_number for details.
6. See Table 4 for VCC2 and VCC3.
5.1 Thermal Specifications
5.1.1 Thermal Diode
The Celeron M processor incorporates two methods of m onitoring die temperatu re, the
Intel Thermal Monitor and the thermal diode. The Intel Thermal Monitor (detailed in
Section 5.1) must be used to determine when the maximum specified processor
junction temperature has been reached. The second method, the thermal diode, can be
read by an off-die analog/digital converter (a thermal sensor) located on the
motherboard, or a stand-alone measurement kit. The thermal diode may be used to
monitor the die temperature of the processor for thermal management or
instrumentation purposes but cannot be used to indicate that the maximum TJ of the
processor has been reached. When using the thermal diode, a temperature offset v alue
must be read from a processor Model Specific register (MSR) and applied. See
Section 5.1.2 for more details. Please see Section 5.1.3 for thermal diode usage
recommendation when the PROCHOT# signal is not asserted. Table 18 and Table 19
provide the diode interface and specifications.
Note: The reading of the external thermal sensor (on the motherboard) connected to the
processor thermal diode signals, will not necessarily reflect the temperature of the
hottest location on the die. This is due to inaccuracies in the external thermal sensor,
on-die temperature gr adients between the location of the thermal diode and the hottest
location on the die, and time based variations in the die temperature measurement.
Time based variations can occur when the sampling rate of the thermal diode (by the
thermal sensor) is slower than the rate at which the TJ temperature can change.
PDSLP
Deep Sleep Power at:
WAt 35°C,
Note 2,5,6
390 VCC2 8.8
380 VCC2 8.8
370 VCC2 8.8
360J VCC2 8.8
360 1.260 V 8.8
350J VCC2 8.8
350 1.260 V 8.8
383 VCC3 1.4
373 VCC3 1.4
353 0.940 V 1.4
TJJunction Temperature 0 100 °CNotes 3, 4
Table 17. Power Specifications for the Celeron M Processor (Sheet 2 of 2)
Thermal Specifications and Design Considerations
66 Datasheet
Offset between the thermal diode based temperature reading and the Intel Thermal
Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic
mode activation of thermal control circuit. This temperature offset must be taken into
account when using the processor thermal diode to implement power management
events.
5.1.2 Thermal Diode Offset
A temperature offset value (specified as Toffset in Table 19) will be programmed into a
Celeron M processor Model Specific Register (MSR). This offset is determined by using a
thermal diode ideality factor mean value of n = 1.0022 (shown in Table 19) as a
reference. This offset must be applied to the junction temper ature read by the thermal
diode. Any temperature adjustments due to differences between the reference ideality
value of 1.0022 and the default ideality values programmed into the on-board thermal
sensors, will have to be made before the above offset is applied.
NOTES:
1. Intel does not support or recommend operation of the th ermal diode under reverse bias.
Intel does not support or recommend operation of the thermal diode when the processor
power supplies are not within their specified tolerance range.
2. Characterized at 100°C.
3. Not 100% tested. Specified by design/characterization.
4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by
the diode equation:
IFW=Is *(e(qVD/nkT) -1)
Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k =
Boltzmann Constant, and T = absolute temperature (Kelvin).
V alue shown in the table is not the Celeron M processor thermal diode ideality factor. It is a
reference value used t o c a lculate the Celeron M thermal diode temperature offset.
5. The series resistance, RT
, is provided to allow for a more accurate measurement of the
diode junction temperature. RT as defined includes the pins of the processor but does not
include any socket resistance or board trace resistance between the socket and the
external remote diode thermal sensor. RT can be used by remote diode thermal sensors
with automat ic series resistance cancellation to calibrate out this error term. Another
application is that a temperature offset can be manually calculated and programmed into
an offset register in the remote diode thermal sensors as exemplified by the equation:
Terror = [RT*(N-1)*IFWmin]/[(no/q)*ln N]
6. Offset value is programmed in processor Model Specific Register.
Table 18. Thermal Diode Interface
Signal Name Pin/Ball Number Signal Description
THERMDA B18 Thermal diode anode
THERMDC A18 Thermal diode cathode
Table 19. Thermal Diode Specification
Symbol Parameter Min Typ Max Unit Notes
IFW Forward Bias Current 5 300 µA Note 1
Toffset Thermal Diode Temperature
Offset -4 11 °C 2, 6
nReference Diode Ideality Factor
Used to Calculate Temperature
Offset 1.0022 Notes 2,
3, 4
RTSerie s Resist anc e 3.06 Ω2, 3, 5
Datasheet 67
Thermal Specifications and Design Considerations
5.1.3 Intel® Thermal Monitor
The Intel Thermal Monitor helps control the processor temperature by activating the
TCC when the processor silicon reaches its maximum operating temperature. The
temperature at which Intel Thermal Monitor activates the thermal control circuit is not
user configurable and is not software visible. Bus traffic is snooped in the normal
manner, and interrupt requests are latched (and serviced during the time that the
clocks are on) while the TCC is active.
With a properly designed and characterized thermal solution, it is anticipated that the
TCC would only be activated for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
periods of TCC activ ation is expected to be so minor that it would not be detectable. An
under-designed thermal solution that is not able to prevent excessive activation of the
TCC in the anticipated ambient en vironmen t ma y cause a noticeable performance loss,
and may affect the long-term re liability of the processor. In addition, a thermal solution
that is significantly under designed may not be capable of cooling the processor even
when the TCC is active continuously.
The Intel Thermal Monitor controls the processor temperature by modulating (starting
and stopping) the processor core clocks when the processor silicon reaches its
maximum operating temperature. The Intel Thermal Monitor uses two modes to
activate the TCC: Automatic mode and On-Demand mode. If both modes are activ ated,
Automatic mode takes precedence. The Intel Thermal Monitor Automatic mode
must be enabled via BIOS for the processor to be operating within
specifications. The automatic mode called Intel Thermal Monitor 1 This mode is
selected by writing values to the model specific registers (MSRs) of the processor. After
Automatic mode is enabled, the TCC will activate only when the internal die
temperature reaches the maximu m allowed value for operation .
When Intel Thermal Monitor 1 is enabled, and a high temperature situation exists, the
clocks will be modulated by alternately turning the clocks off and on at a 50% duty
cycle. Cycle times are processor speed dependent and will decrease linearly as
processor core frequencies increase. Once the temperature has returned to a non-
critical level, modulation ceases and TCC goes inactive. A small amount of hysteresis
has been included to prevent rapid active/inactive transitions of the TCC when the
processor temperature is near the trip point. The duty cycle is factory configured and
cannot be modified. Also, automatic mode does not require any additional hardware,
software drivers, or interrupt handling routines. Processor performance will be
decreased by the same amount as the duty cycle when the T CC is active, howeve r, with
a properly designed and characterized thermal solution the TCC most likely will never
be activated, or only will be activated briefly during the most power intensive
applications.
The TCC may also be activ ated via On-Demand mode. If bit 4 of the ACPI Intel Thermal
Monitor Control Register is written to a 1, the TCC will be activated immediately,
independent of the processor temperature. When using On-Demand mode to activate
the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the
same ACPI Intel Thermal Monitor Control R egister. In automatic mode, the duty cycle is
fixed at 50% on, 50% off, however in On-Demand mode, the duty cycle can be
programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments.
On-Demand mode may be used at the same time Automatic mode is enabled, however,
if the system tries to enable the T CC via On-Demand mode at the same time automatic
mode is enabled and a high temperature condition exists, automatic mode will take
precedence.
An external signal, PROCHOT# (processor hot) is asserted when the processor detects
that its temperature is above the thermal trip point. Bus snooping and interrupt
latching are also active while the TCC is active.
Note: PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep, Deep
Sleep, and Deeper Sleep low power states (internal clocks stopped), hence the thermal
diode reading must be used as a safeguard to maintain the processor junction
Thermal Specifications and Design Considerations
68 Datasheet
temperature within the 100°C (maximum) specification. If the platform thermal
solution is not able to maintain the processor junction temperature within the
maximum specification, the system must initiate an orderly shutdown to prevent
damage. If the processor enters one of the above low power states with PROCHOT#
already asserted, PROCHOT# will remain asserted until the processor exits the Low
Power state and the processor junction temperature drops below the thermal trip point.
If automatic mode is disabled, the processor will be operating out of specification.
Regardless of enabling the automatic or On-Demand modes, in the event of a
catastrophic cooling failure, the processor will automatically shut down when the silicon
has reached a temperature of approximately 125°C. A t this point the FSB signal
THERMTRIP# will go active. THERMTRIP# activation is independent of processor
activity and does not generate any bus cycles. When THERMTRIP# is asserted, the
processor core voltage must be shut down within a time specified in Chapter 3.
§